Hello, I've been using the ADS52J90's JESD interface at a fairly slow sampling rate and was looking to increase it to the fastest the chip allows. The equation for determining JESD204B speed is:
Line rate = M x N' x (10/8) x Fs / L
Where M is the number of ADCs, N' is the bits per sample, 10/8 is for 8b10b encoding, Fs is the sample rate, and L is the lanes used. So if:
M is always 16
N' is 16 if I turn on the SING_CONV_PER_OCT bit
Fs is 80 MHz in 12 bit mode
L is 2 to interface with my FPGA
According to this, the JESD line rate will be 12.8 Gbps. But on the first page of the datasheet, the ADS52J90 says that it has a 5 GHz JESD interface. Will my settings work? Or do I need to check my settings to make sure I stay under a 5 GHz line rate when using the JESD interface? In my example, even turning off the SING_CONV bit so N' is 12 means that the line rate would be 9.6 Gbps, still apparently over the chip's limit.