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DAC5682Z: Disabling updates of the FIFO tap

Part Number: DAC5682Z

Is there any way to fix the tap (i.e. prevent any further adjustmentof the tap being used)  used from the DAC5682Z  FIFO once a SYNC event has been generated? The DLL is not being used in this applicatio which runs at about 100 MHz.

  • Hi Derek,

    Which tab are you describing here? can you please clarify you request in little bit in more detail.

    Regards,

    Neeraj

  • The DAC5682 has an internal data FIFO; the data fed to the analogue section is taken from a tap from the FIFO controlled by the internal workings of the DAC5682. This can be controlled externally to a certain extent via bits 2:0 of the CONFIG1 register. The offset used appears to be dynamically controlled internally by the DAC. Can the internal control be disabled (following a SYNC event) via the serial interface? What is the mechanism that triggers any internal adjustment ( e.g. noise on the SYNC input or data clock inputs)?

  • Hi Derek,

    Bit 2:0 are used to set the initial offset for the FIFO write and read pointer. But there is no way to disable it via serial control.

    Regards,

    Neeraj

  • Just to confirm: the serial bus can only be used to set the *initial* value of the tap. What happens to the tap setting after that is up to the DAC's internal control algorithms? 

  • Hi Derek,

    Yes your statement is correct  the serial bus can only be used to set the *initial* value of the tap. What happens to the tap setting after that is up to the DAC's internal control algorithms.

    Regards,

    Neeraj