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ADC12DJ3200: The JESD link fails randomly

Rajesh khanna
Intellectual 690 points
Part Number: ADC12DJ3200

Hi,

Our configuration:

line rate : 6.25 Gb/s, Ref clock : 156.25 MHz, Sysref : 19.53125 MHz.

Jmode: 5, F = 0 & K = 32.

Initialization is some time successful some time fails randomly.

When the link is established properly the ADC operation is ok.

When it fails we find strange, some times sync pin is always low and some time sync pin is toggling.

How to establish the link reliably always, please provide some suggestions.

Regards,

Rajesh khanna.

  • 0
    TI__Mastermind 20130 points

    Hi Rajesh,

    There are a couple of things you can look into for us.

    First, if your you need to have a stable digital power on the VD11 pins. 

    Second, you can try using the PRBS pattern and capture the eye diagram. You need to look at this per lane.

    If the signal integrity of the trace lanes are not adequate for this high rate of data, then the eye will start to collapse over time.

    Regards,

    Rob