ADS122C04: Minimum RESET Time

Hi Don,

I apologize for the delayed response.  There are two considerations.  The first one is the start of communication following the rising edge of the RESET pin.  This is shown as 100ns in the datasheet as you pointed out at the original post.  The second consideration is not clearly specified and that is the timing as to when you can reconfigure the ADS122C04 following the RESET pin going high. This actually differs from start of communication.

Note that the ADS122C04 is ACKing and recognizing that communication has started to the ADS122C04.

This demonstrates that communication is possible at this point.  However, although the communication is possible it does not mean that the device is ready to be configured.  Unfortunately I cannot find specific design information regarding this timing and will have to attempt to contact the designer for additional information.  Most likely we will need to update the datasheet with additional timing information.  It would appear that the timing from the RESET pin going high to start of communication for a device configuration is only valid when using Standard mode timing.  I will respond again when I receive a clarification.

The ADS122U04, although using a different interface, is very similar in operation to the ADS122C04.  The ADS122U04 timing requires a minimum delay of 80us.  Based on your your 200kHz timing experiment the delay time appears to be similar.  The device decode for the command takes place on the bit 7 of the 8 bit command.  This would occur approximately on the 16th clock from the beginning of communication or approximately 80us from the first clock.

I believe that by delaying the initial delay from 4us to 84us should be sufficient for operating in Fast Plus mode.  I calculated from 200kHz period (5us) times 16 clocks plus 4us initial delay which equals 84us which appears to be working. You could increase this slightly if you want a little guard band.

Best regards,

Bob B

Hi Don,

This can become a complicated answer.  The designer says that if the NACK is ignored that the register write would still take place.  So the communication does work, just not as expected.  Essentially it takes 80us from the rising edge of the RESET pin until all of the internal trim information is read from the device.  During this time communication is possible, but there is a hold on the ACK signal for commands until this update period ends.

So to get an ACK on the command, you would need to make sure that 80us has passed prior to the ACK signal time frame.  This is the same delay required for the ADS122U04, so my theory was correct that I posted previously.

We need 80us delay prior to the WREG decode.  We are using 1MHz clock for SCL, and each clock period would be 1us.  After 16 clock periods (16us) the WREG command will decode. 80us - 16us = 64us, so you would require at least 64us delay to meet the 80us total time to receive the WREG ACK.  This is assuming perfect timing and no clock drift.

The 80us is based on all process corners and operating temperatures.  So it could be possible that a shorter time delay would work on some devices at room temperature, but 80us is the safe time and should be the time used for calculation to ensure the ACK.

Best regards,

Bob B