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The abs max limit of 3.6V limit is about 600mV down from the voltage which will turn ON the positive diode. We want to discourage customers in applying the max voltage on analog input pins. Therefore a margin is kept. But how big should the margin be? It should be such that device allows sufficient overload. For example, if the common mode is 1.5V and full scale is 2Vpp, INP and INM swing from 1V to 2V when device output reaches full-scale limit. Let’s now allow common mode to vary, say by +500mV (which is what this device can be stretched to with some performance). The INP and INM will now swing from 1.5V to 2.5V. Now, add 10dB overload. This means INP and INM will swing from 0.4V to 3.6V. Since 3.6V is hard limit beyond which device may be damaged, momentary 10dB overload is the max overload device can tolerate with no damage.
I'm confusing what you explained, sorry. Could you please explain again to answer below question?
Is the max AVDD 2.1 V, why AVDD become 3.9V at the attached figure?
Where is the positive diode located? I couldn't see it in the datasheet, such as Figure137. Is the 4.2V (3.6V + 600mV) a forward voltage of the diode?
You didn't mentioned about "1.9V" even the ppt. When does this value have meaning?
What customer concerns are the situation that analog inputs are existing before AVDD applied. Is there any needed to protect input pins before AVDD applied?
Sorry for the confusion. I was referencing the ADS62P49 data sheet by accident. For the ADS4225, the absolute max applied analog input voltage should be stated as “-0.3V to minimum (2.1V, AVDD + 0.3V)”. This was stated in the data sheet as (1.9V, AVDD + 0.3) to give extra head room.
The diode mention is the ESD protection diode and it is not shown in the data sheet. This diode would turn on around 300mV above max AVDD. This would be around 2.4V since AVDD absolute max is 2.1V. To allow for some headroom, 300mV was added to prevent the diode from ever turning on if the AVDD was at the max value.
I am waiting to hear back from design regarding the other question.
What customer concerns are the situation that analog inputs are existing before AVDD applied. Is there any needed to protect input pins before AVDD applied?
As long as the input on INP/M does not exceed the absolute value (2.1V) you should be ok.
It seems that 2.1V is the absolute maximum value of AVDD or DRVDD. For the INP/M, the absolute max value is written as "Minimum (1.9V, AVDD+0.3V)". I would like to make it sure which value, 1.9V or AVDD+0.3V, will be applied?
Regards,
