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ADC161S626: max tcl - SCLK Low Time

Jens Tyslik
Intellectual 1590 points
Part Number: ADC161S626

Hi, 

the data from ADC161S626 is read in blocks of 8 bit. Between these reading processes is a break of ~ 5µs, in which the clock signal is low. Could this lead to an issue? In the datasheet there is only a min. SCLK Low Time of tcl = 20 ns mentioned. Is there a max. time between the readings, that should not be exceeded when reading the converted data through SPI? 

thanks, 
Jens

  • 0
    TI__Mastermind 39530 points

    Hello Jens,

    The ADC161S626 uses the SCLK for the conversion clock.  This places a maximum SCLK period limit due to leakage currents inside the device, which is specified in the datasheet as a minimum SCLK frequency of 1MHz, or 1uS max period.

    A conservative interpretation of this spec would place a maximum SCLK idle low time of 500nS.  5uS will probably work at room temperature, but at higher ambient temperatures the noise and INL specs may be degraded.

    Regards
    Keith Nicholas
    Precision ADC Applications