Hi,
In ADS42B49 datasheet, all following figures shows LVDS DDR timing and gives information about Even and Odd data bits position with respect to CLKOUTP signal.
Figure 38, Figure 40 and Figure 41
Seems Even data bits are output at falling edge of CLKOUTP, Odd bits are output at rising edge of CLKOUTP.
Figure 44
Says Even data bits (D0, D2, D4, and so forth) are output at the CLKOUTP rising edge and the odd data bits (D1, D3, D5, and so forth) are output at the CLKOUTP falling edge)
Which one is correct?
Mustafa
