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Original question:

ADS62P25 single-ended input

ADS62P25: the maximum speed of the CMOS and LVDS interface

Yanni Li
Intellectual 1960 points
Part Number: ADS62P25

HI,team

The datasheet doesn‘t give a clear indication about the maximum speed of the CMOS and LVDS interface

In both the interface what is the maximum speed that i can achive? Thank you.

  • 0
    TI__Guru* 91947 points

    Yanni,

    Since the max sample rate for this device is 125Msps, the max rate for the CMOS interface is 125MHz. Since the LVDS is DDR, the max rate for this 250MHz.

    Regards,

    Jim.

  • 0 in reply to jim s
    TI__Intellectual 1960 points

    Thank you for the quick response.

    Here are the inquiry from my customer in verbatim: 

    “In the attached image am mentioning two options.

    Option 1:
    Am using only ADS62P25 inter termination of 100 ohms.
    There wont be any external termination.

    Option 2:
    Am using on ADS62P25 inter termination of 100 ohms and also providing an external termination of 100 ohms in the FPGA side.

    Option 3:
    Am using on ADS62P25 inter termination of 100 ohms and also providing a 100 ohms termination inside the FPGA.

    I would like to know all these 3 cases which option will provide better result during eye diagram capture.”

    Thank you.

  • 0 in reply to Yanni Li
    TI__Guru* 91947 points

    Yanni,

    LVDS requires 100 Ohm termination and the closer the termination resistor can be to the load, the better. This would make option 3 your best choice.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Intellectual 1960 points

    Thank you for your awswer