This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1220: - PCB design.

Part Number: ADS1220

Hello everyone!

My question about correct connect AGND to DGND in the battery device.

First of all - schematic diagram:

analog part of PCB (both sides):

Is it correct design for minimize noise from Load Cell Bridge ? May be should be only a routed wire (not copper pour ) ? Could you please give an example how to correct route pcb.

Thank you.

  • Hi Alex,

    Welcome to the E2E forum!  The ADS1220 datasheet in section 11.2 shows a layout example using a single-ground plane and this is the recommendation.  There are also layout recommendations in section 11.1.  In the paragraph under Figure 86 it states the following:

    The use of split analog and digital ground planes is not necessary for improved noise performance (although for thermal isolation this option is a worthwhile consideration). However, the use of a solid ground plane or ground fill in PCB areas with no components is essential for optimum performance. If the system being used employs a split digital and analog ground plane, TI generally recommends that the ground planes be connected together as close to the device as possible. A two-layer board is possible using common grounds for both analog and digital grounds. Additional layers can be added to simplify PCB trace routing. Ground fill may also reduce EMI and RFI issues.

    Take a look at the bridge circuit in the datasheet in section 9.2.3 that shows a bridge application.  You may also find the PCB layout guidelines FAQ helpful.

    If you feel that it is necessary to split the planes I would suggest placing the 0 Ohm resistor on the bottom-side of the PCB as shown:

    What happens when you split the ground path is you are forcing return currents back across the split.  Most digital currents these days are relatively low power and usually do not cause an issue.  The use of ground traces can be an issue as now instead of having a low impedance ground you increase the impedance.  Also analyze the DC path of the supply.  AVDD current comes from the REF50xx and follows over the GND of the digital supply.  Also, I do not see any routing of the digital signals.  So it is difficult to determine the effectiveness of supplying from the reference and the supply path relative to the digital signals.

    It appears that you are using CS as a gate for the supplies.  This will not work quite the way you intend.  If the digital supply is not powering the ADS1220 but you have a voltage applied to the digital inputs (such as CS high), you will be exceeding the absolute maximum input voltage ratings of the ADS1220.

    Also when powering the analog supply from a reference instead of an LDO or linear regulator you may find that the reference may not be able to supply sufficient current to both the ADC and the bridge.  There are periodic currents required by the ADC that can peak into the mA for short durations.  It appears that you have a large bulk reserve capacity connected to the output of the reference, but you could still see some current issues if the bridge draws significant current.

    If the supply is 3V, then the largest reference output available is 2.5V for the REF50xx.  This limits significantly the output of the load cell and may be difficult to overcome the noise from such a low signal input.  As the measurement is ratiometric, the noise and drift of the excitation source will cancel out of the measurement, so I would suggest that you consider using a single source of supply voltage and remove the split.

    As far as the analog inputs, you want C11 to be 10x greater in value than C12 and C14 to prevent differences in filter components creating a difference voltage at the input.  The signal trace should also flow into the capacitors directly as opposed to just a trace to the capacitors.  This allows the capacitor to have a greater impact with lower inductance.

    Best regards,

    Bob B

  • Thank you for help.

    In this case i can not use higher than 2.5 voltage for AVDD without step up, because device battery powered (LiSoCl2 - 3,6v )
    This device - RF -  LC bridge reader

    I changed some elements in schematic for direct connection DVDD to LDO, and periodic power on AVDD (one time in 30 seconds for measuring)

    Also add vias for isolate ADC and Vref,  AVSS - connected to GND 3 points only (mark yellow on pcb)

    Is it will better for this case ?

  • Hi Alex,

    I'm not understanding why the three points shown only connect to the ground on the bottom-side of the board.  I would also advise to make as many of the traces run on the top-side of the PCB as well.  Although you have added many ground vias, the return current would not need to steer around traces when limiting the long runs on the bottom of the board.

    Also, the bypass caps for the analog and digital supplies to the ADS1220 should be placed as close as possible to the input pins of the ADS1220 otherwise the inductance of the traces will affect the transient currents  and can create a ringing at those pins.  Also, it appears that C17 is only partially on the board (only 1 pad).

    I realize that there is considerable off time, but you may want to consider the amount of charge required when powering the analog supply on and off as there is significant capacitance where charge may deplete.  You may find that using the POWERDOWN command may be more efficient than powering up and down the ADS1220.

    Best regards,

    Bob B

  • Thank you for help !