Other Parts Discussed in Thread: LMK1C1108
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
You should be able to drive 5 ADS127L01 plus FPGA with a single ADS127L01, provided that the board capacitance is not too high and the devices are close together. Each ADC digital input will have about 2pF of capacitance and the SCLK/FSYNC outputs should be limited to a total of about 20pF. However, if you have long boards traces between the devices, then you could have signal integrity issues. Since we do not have a specification for the maximum fanout, I would suggest adding a buffer to both the SCLK and FSYNC lines on the controller ADC to ease the driving requirements for this many ADC's plus the FPGA.
Regarding your question 2, as long as you properly synchronize all ADC's, then the FSYNC and SCLK of each ADC will be aligned with each other. Figure 86 and Table 14 provide the timing requirements to achieve this operation mode.
Regarding question 3, there is a delay between START falling edge and DOUT falling edge. However, we do not specify this, and it is not important to properly synchronize multiple devices. After a SYNC, RESET, or MODE change in Frame Sync Mode, you should look for a low-to-high transition on DOUT to determine when data are fully settled.
One other suggestion, as long as you can meet the timing requirements, it might be easier to use frame-sync slave mode for all ADC's and let the FPGA generate the SCLK and FSYNC waveforms. In this case, most FPGA IO pins can drive a lot of capacitance, so you should not need any additional buffers. Also note in Figure 104 of the datasheet that the DIN should be connected to ground instead of the FPGA.
Precision ADC Applications