This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS131A04EVM: Problems with receiving ACK on UNLOCK

Part Number: ADS131A04EVM
Other Parts Discussed in Thread: ADS131A04, ADS1018


I am not able to receive an ACK on UNLOCK.

I was able to trace the TIVA interaction with the ADS131a04, and it showed the proper responses to commands. 

When I connect an external microprocessor and try to drive the SPI lines, I receive READY, but I do not receive a 0x655 from UNLOCK.

I have 6-inch lines between my board and the EVM: Ground, MOSI, MISO, CS, SCLK.

I have set MO,M1,M2 for 32-bit words, and switched S4 to manual.

I have put a jumper on JP1 to disable processor.

I send "00000000" and see READY.

I send "06550000" and do not see anything other than READY.

I am using 12.5 MHz SCLK, and the waveform looks correct, except for some "glitches" (However, I was able to connect to ADS1018 with same setup and I was able to receive data.)

Not sure what else to say - I know that the SCLK waveform is not 50% duty cycle (more like 30%) - if I am able to get to 50% would that help?

Also, I am thinking of using twisted-pair for each of the 4 connections. I did twist GND with SCLK and that appeared to clean up noise on that line.

Given that the input clock to the device is 16.384 MHz, is 12.5 MHz too fast?


Todd Anderson

  • Success: UNLOCK acknowledged

    I had to make duty cycle 50% on SCLK. I also reduced SCLK to 6.2 MHz. This is 32-bit SPI.


    I thought MISO would extend zeroes into full width on reply. It did on 24-bit, but on 32 bit it looks like it stopped.

    More questions to come - I will be moving on to initialization of registers. I will initially try to match the EVM, will probably not do CRC initially.


    Todd Anderson

  • Hi Todd,

    Thank you for your post - glad you already figured it out! :)

    Yes, the SCLK duty cycle could make a difference here. The period of a 12.5-MHz SCLK is 80 ns, and a 30/70 duty cycle would make either the high or low pulse only 24 ns. The minimum SCLK pulse width depends on the interface mode, IOVDD supply, and the number of devices sharing the bus. You can confirm the minimum SCLK pulse width for your configuration using the Timing Requirements tables in the data sheet (7.6 - 7.11).


  • Todd Anderson3 said:
    I thought MISO would extend zeroes into full width on reply. It did on 24-bit, but on 32 bit it looks like it stopped.

    I'm not sure what could be going on here. Each word should be extended to fill the preset word length of 24 or 32 bits. If Hamming Code is enabled, the last 8 bits of the data words will contain the Hamming Code result. Hamming code does not affect the status word, so those should always be extended with 0s.