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ADC16V130: RE: ADC16V130 Clock architecture

Part Number: ADC16V130
Other Parts Discussed in Thread: DS25BR440

Hi Team,

In our exiting project we have used ADC and FPGA both are placed in the same board but current architecture we are planning backplane method.

In new system we are going with modular concept Like FPGA and ADC having different boards connected through backplane We required clock architecture suggestion for our project.

I have attached pdf for existing and current clock architecture. Kindly review our architecture and provide your feedback. Please suggest any other method to follow board to board clock architecture.

Clock Diagram.pdfThanks

Naveen P

  • Hi Naveen,

    The attached pdf is a great way to help solve this new architecture. This will work.

    Regards,

    Rob

  • Hi Rob,

    Thanks for your response. Similarly I have one query on ADC output data and DAC Input data,

    ADC output data is going to FPGA through backplane, Similarly FPGA LVDS output data is going to DAC .through BP, Due to length constraints we are planning to place the LVDS BUFFER in between ADC to FPGA  and FPGA to DAC.

    Please find the below attached block diagram for your reference. Kindly verify our block diagram and provide your feedback or please suggest any other method is there to implement.

    LVDS Buffer part we are going to use is, DS25BR440.

    Thanks for your support

    Regards,
    Naveen P

    ADC_DAC_PATH_UPDATED.pdf

  • Hi Naveen,

    What is the total length from the ADC outputs to the backplane to the FPGA? If only 5-6inches, then you probably don't need the buffer.

    Otherwise, if you feel you need the buffer, then this will work just fine.

    Regards,

    Rob