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DAC43608: SDA Spikes

Part Number: DAC43608

Hello team,

I have a couple of application questions about DAC43608.

Please find the internal link here for schematic and detailed issue description. (Please connect to VPN for download)

Q1. The SDA has spikes as shown in the attached. Is this caused by the delay from SCL falling edge to output ACK?

Q2. DAC43608 is operating in FastPlusMode. As it is operating in 50% duty with 1MHz frequency, it is on the edge with respect to datasheet requirements

fSCLK=1MHz(Max.) and tLOW =0.5us(Min.). Do you think attached waveforms are OK? If I need to slow down the data rate, please let me know.



  • Hi Itoh-san,

    Are you able to communicate with the device? I do think the spike on SDA is coming from the FPGA releasing the SDA line before the DAC pulls it low, but this should not be an issue. 

    If it is not possible to adjust the duty cycle, it may be safest to slow the SCL by a few ns. 

  • Hello Katlynne-san,

    Could you please answer your thought about the attached waveforms?

    As the SCL comes from FPGA, I can control the duty cycle.
    Do you recommend it's better to set high duty cycle to 40% (TON=400ns) for safety?

    I'd appreciate if you let me know the allowable f_SCLK and t_LOW more specifically (I don't mean I need the value TI can guarantee. I just want to make sure my system works properly).



  • Hi Itoh-san,

    Yes, setting the duty cycle to 40% would guarantee that the Toff is well above the 500ns minimum limit. Make sure the set up/hold times as well as the other timing requirements are still met. f_SCLK and t_LOW just need to be within the min/max values given in the datasheet. A few ns above the minimum limit for t_LOW will suffice. The attached waveforms look ok besides the t_LOW being very close to the minimum limit. Decreasing the duty cycle to 40% will ensure the t_LOW is safely above this limit. The spike on SDA should not have any effect on the communication with the device.