I have a couple of application questions about DAC43608.
Please find the internal link here for schematic and detailed issue description. (Please connect to VPN for download)
Q1. The SDA has spikes as shown in the attached. Is this caused by the delay from SCL falling edge to output ACK?
Q2. DAC43608 is operating in FastPlusMode. As it is operating in 50% duty with 1MHz frequency, it is on the edge with respect to datasheet requirements
fSCLK=1MHz(Max.) and tLOW =0.5us(Min.). Do you think attached waveforms are OK? If I need to slow down the data rate, please let me know.