Hi Tom,
I also encountered the same issue when I read more than one channels sequentially using a FPGA. The results were different when compared to reading any single one channel at a time. My questions are as follows:
1) Does increasing the number of consecutive readings of the same channel (before switching to the next channel) improve the accuracy of the results?
2) Or should I simply reduce the SPI clock during the track phase (the first 3 cycles of the SPI frame) to allow a longer settling time for the internal ADC capacitor?
Hope to hear from you soon. Thank you in advance.
Regards
Melvin