Other Parts Discussed in Thread: ADS5263
The first question is about the memory capacity:
Based on ADS5263EVM+TSW1400, when the signal is sampled through 4 channels at 10MHz, the memory capacity should be 2^30 / (4*2) = 2^27, that is, 134217728 samples theoretically. However, it works a few times, more often fails. It seems irregular.
The second question is about the sampling frequency:
As a pipeline ADC, ADS5263 works at the beat of the input clock, thus we reduce the clock frequency to 6MHz in order to lengthen the sampling time. However, sometimes it works well, sometimes it doesn't. Especially when the clock frequency is lower than 5MHz, there are burrs on the output curves. What I wanna know is the actual minimum sampling frequency or if it is possible to reduce the clock frequency below 10MHz.