This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC8811: Related to your answer to:DAC8811: DAC output update timing

Part Number: DAC8811

Related to your answer to:DAC8811: DAC output update timing

The previous answer states that if the data is invalid it is discarded.  What is invalid data in this case?  Does the DAC8811 count clock edges while /CS is low to verify that 16 (and only 16) have been received in the data transfer?  It appears that what ever data is in the serial register at the time the /CS transitions from low to high will be applied to the DAC output register.

  • Hi Tim,

    My understanding is that the device does count edges, if they to not equal 16, the data is ignored when CS transitions low to high.  

    Are you seeing different behavior?



  • Hello Paul,  Thank you for your response.  I'm confused over the documentation in the datasheet.

    Pg 14

    Table 1     "/CS ↑+ Shift register data transferred to DAC register."

    Pg 15 

    "On the 16th rising edge of the serial clock, the last data bit is clocked in and the programmed function is executed (what is this).
    At this point, the CS line may be kept low or brought high. In either case, it must be brought high for a minimum of 20 ns before the next write sequence so that a falling edge of CS can initiate the next write sequence."

    So it seems that either the 16 clock edge or the /CS positive transition will cause the output to update.  I'm betting on Table 1 being the correct information.  We also use a very similar part (AD5543 which appears to be pin compatible) and it can accept an undefined length serial stream.  It only uses the last 16-bits clocked in and updates on the positive transition of /CS.

    I don't have the capability to experiment in my system so I can't change the number of clock pulses or extend the /CS duration.  I was hoping the TI technical staff could step in on this one and explain the internals of the DAC8811.

  • Hi,

    Its not either 16th Clock edge or /CS positive transition. Data will be loaded into the DAC register only when there is the rising edge on the /CS line with minimum 16 SCLKs.  

    see additional information in page no: 4 for pin functions SDI : Serial register input; data loads directly into the shift register MSB first. Extra leading bits are ignored.

    Table 1 is the correct operation of the device.

    I think this clarifies your doubt, any extra leading bits will be ignored



  • Thank you to all that have contributed.  The subject datasheet has proven to be a puzzle to both junior and senior personnel.  I find the senior personnel assume the device operates in a logical manner similar to other SPI devices.  Basically there is a belief that the device accepts data while the /CS is active and that data is transferred to the output following the positive transition of /CS.  The senior personnel don't seem to be concerned over the number of clocks and just assume it works as advertised.  On the other hand junior engineers don't have a preconceived method of operation.  They try to interpret the datasheet which leads to conflicts.  Wouldn't it be great if there were direct statements similar to the following the datasheet?

    "A data transfer begins on the negative transition of /CS and terminetes on the positive transtion of /CS.  Data transfers with less than 16 positive clock transitions will be ignored (analog output will not change).  Data transfers with 16 or more positive clock transitions will ignore excess leading data bits and transfer the last received 16 data bits to the DAC register (analog output will change) on the positive transition of /CS."

    Also for the case when power is applied when /CS is held at the logical false state:

    "Upon application of power the serial register bit counter will be set to zero and the DAC register will be cleared to an all-zero state." or "The serial bit counter is set to zero upon the negative transition of /CS."

    Since there are applications that utilize both burst and continuous clock modes an understanding of the detailed operation of the interface is necessary.

  • Hi,

    This device works as per SPI interface. So your statements are correct in interpreting the datasheet.

    What I meant was if there are not enough clocks ( min 16), the data will be ignored and if there more than 16 clocks and data, extra leading bits will be ignored by the device. All SPI transactions start with /CS going low.

    We will update the datasheet to avoid this confusion in future. Thanks fr your valuable comments.