Other Parts Discussed in Thread: ADS42LB69EVM,
I was planning to use ADS42LB69EVM with TSW1400evm.
I am thinking of using AWG2021 as the clock source for the ADC.
It is mentioned that the Max clock freq is 250 MHz and Vpp should be 1 in the user guide.
For AWG2021, under the clock generator section: Freq range is 10-250 MHz and in the External Outputs Section: Amplitude Range is 0.05V to 5 Vp-p into 50 ohms.
When I referred to the Layout design of ADC- FPGA interface, the resistor is not a separate attribute but included in the Layout trace itself.
Can you help me with the input impedance and also if this clock source works well.