Other Parts Discussed in Thread: ADS54J42,
Here is the premise of my question:
Overview: I want deterministic sample collection after every power up. Here is an example scenario: Say that I power up the device and it initializes and starts driving digital data. Per the datasheet, the edge of the signal the my FPGA uses as a clock (DRY) is undetermined from power up to power up. I’m concerned that this undetermined signal edge will make the first sample I collect vary by a sample. My goal is to not have any sample variation.
My question is: I believe I'll have at least one sample variance when using this part; is there a workaround to make it deterministic?
Here is more information that may help in understanding the scenario: assume two identical timelines when powering up the ADC.
- Question: With ADC output clock not being deterministic for its edge, How can I know what sample is going to be received first from power up to power up when I decide to start collecting?
- Assuming data input A,B,C,D,E come in on every edge; assume DRY has rising edge on B and D
- I have a DDR receiver that clocks data in on rising and falling edges to capture two samples per clock period. These captured signals go to rising edge ‘capture’ flipflops.
- If start collecting samples on the rising edge of clock, and after power up, a positive edge occurs, my first capture of data will be “B” and then C on the falling edge. My capture flipflops get BC
- Assume rising edge after powerup is A,C,E
- I start sampling on the rising edge of clock, my first sample would be A, or C, not B. so I am off by a sample. My capture flipflops would get AB, or CD, but never BC because the edge is different than the previous power up. Is this understanding correct?
Question: Is there a way around this problem to ensure that I get the same first sample captured every power up if the edge may be different every time? I.e., Is there any way to synchronize the ADC to a known edge on the clock, relative to the incoming sample data. Or, is it just not possible with this part?