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# ADS5474: Does not have have deterministic sample capture due to clock edge uncertainty with each power up. Any workaround?

Here is the premise of my question:

Overview: I want deterministic sample collection after every power up. Here is an example scenario: Say that I power up the device and it initializes and starts driving digital data. Per the datasheet, the edge of the signal the my FPGA uses as a clock (DRY) is undetermined from power up to power up. I’m concerned that this undetermined signal edge will make the first sample I collect vary by a sample. My goal is to not have any sample variation.

My question is: I believe I'll have at least one sample variance when using this part; is there a workaround to make it deterministic?

Here is more information that may help in understanding the scenario: assume two identical timelines when powering up the ADC.

1. Question: With ADC output clock not being deterministic for its edge, How can I know what sample is going to be received first from power up to power up when I decide to start collecting?
1. Assuming data input A,B,C,D,E come in on every edge; assume DRY has rising edge on B and D
2. I have a DDR receiver that clocks data in on rising and falling edges to capture two samples per clock period. These captured signals go to rising edge ‘capture’ flipflops.
3. If start collecting samples on the rising edge of clock, and after power up, a positive edge occurs, my first capture of data will be “B” and then C on the falling edge. My capture flipflops get BC
4. Assume rising edge after powerup is A,C,E
5. I start sampling on the rising edge of clock, my first sample would be A, or C, not B. so I am off by a sample. My capture flipflops would get AB, or CD, but never BC because the edge is different than the previous power up. Is this understanding correct?

Question: Is there a way around this problem to ensure that I get the same first sample captured every power up if the edge may be different every time?  I.e., Is there any way to synchronize the ADC to a known edge on the clock, relative to the incoming sample data.  Or, is it just not possible with this part?

Thank you.

• Brian,

Based on the comment from section 7.3.2 of the data sheet:

“If the synchronization of multiple ADS5474 devices is required, it might be necessary to use a form of the CLKIN signal rather than DRY to capture the data”.

It appears your only option to have deterministic data is by controlling the input clock. I would suggest having a way to turn on an external clock such that the rising edge occurs at a known time every time.

You will probably have to have power applied first before the clock.

You may want submit a post with the high speed clocking forum with help regarding controlling the clock.

Regards,

Jim

• Thank you, I'll have to look into that as an option.

• Hi Jim,

I thought about this a little more.  I'm not sure how that would help me.  I'd need to know the relationship between the ADC input clock and how the ADC starts sampling data.  There also doesn't seem to be a reset signal on the ADC to help determine a 'known' starting point.  Can this be specified somehow?   E.g., after power-up, the first rising edge of the input clock is what captures the first ADC sample? I'm not sure if there are any clock conditioning circuits in the ADC or other internal reset logic that could effect the data collection, etc...

If that could be specified, then perhaps I could create a gated clock to the ADC that could be 'started' for a known relationship...  Is that something TI can provide?

Thanks,

Brian

• Brian,

The designers that worked on this part are no longer with our group and we do not have the manpower right now to investigate the design data base to try and answer your questions. Have you looked in to using one of our newer JESD204B devices that do support deterministic latency, such as the ADS54J42?

Have you looked into purchasing an ADS5474EVM to try and run some experiments to gather this info? The only thing I can think to try is it run a narrow pulse into the analog input that is also sent to an oscilloscope. Monitor the MSB of the ADC with the scope as well. After power is applied, enable the first clock rising edge a know time before the pulse is sent to the ADC and monitor the clock, the pulse and the ADC MSB on the scope.

Regards,

Jim

• Hi Jim,

Thanks for the ideas; I appreciate it.   We're sort of locked into this part right now so changing it would be difficult and implementing JESD would likely require fpga changes as well.     I'll ponder the empirical lab tests; although assuming the test results would be applicable to all parts over PVTemp... might be a little difficult.

I understand what you're saying though.

Thanks,

Brian