In table on page 32 of the April 2016 datasheet, register 0x3A[6] indicates FCLK output will be an LVDS output when set to 1; otherwise, when set to a 0, the output will be CMOS.
On page 24 section 8.3.9, however, the datasheet states:
"...the device output from LVDS to CMOS mode by programming any of the bits DOUT_CMOS, FCLK_CMOS and DCLK_CMOS (0x3A [4,5,6]) to 1."
This appears to contradict the information in the register table for FCLK, which is correct?
Thank you in advance,
Tony
