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DAC80502: Sequential DAC update wait time

Part Number: DAC80502

Hello,

Can you help explain exactly what is meant by "Sequential DAC update wait time"?  If this is a Min, what should we expect as a Max?  Is it referring to the delay from the trigger to the output, or is it related to an internal delay?

Our customer is seeing quite a bit of variability on this when operating a SPI mode.  After Trigger, the delay is sometimes 1.5us, and other times 4us.

Thanks,
Darren

  • Hi,

    Sequential DAC update is time is the minimum time you need to give in between SPI transactions for DAC data update. Meaning, After one DAC update, you need to wait for min 1uS before initiating DAC data update. This is because we have internal T&H circuit for reducing code to code glitch.

    This explained in the below e2e post.

    https://e2e.ti.com/support/data-converters/f/data-converters-forum/873137/dac60501-dac-settling-time-clarification

    Right after the DAC latch the data (rising edge of CS), a sub circuit called the "track and hold" is enabled.  This basically blocks the output from seeing the internal ladder from changes.  This is to reduce the code-to-code glitch.  After a few hundred nanoseconds (nominally), the hold releases and the output is connected.  At that time you will see a small glitch.  You can see that in the glitch diagram that the output does not change in the first ~400ns.  This is the track and hold time.  

    tDACWAIT is saying that you should not trigger another latch event until the TnH is complete.  Across temperature, supply voltages, and process the track and hold time can vary, so tDACWAIT is a bit conservative. 

    Regards,

    AK