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ADS5294: Abnormal non-linearity in the converter output

Part Number: ADS5294


Dear all,

I'm using an ADS5294 ADC in order to sample the output of an ASIC.

We need to sample stable DC levels generated by the ASIC output multiplexer (staircase)

We are concerned about the non linearity of the ADC. 

I connected the ADC to a Kintex7 FPGA and one of the 8 analog input is connected to a ramp generator that swing in the full dynamic of the ADC. 

I have a true random pulse generator that trigger the FPGA to sample a point of the ramp and histogram it. In this way i should generate a white distribution.

I would expect a perfect white distribution but i got a distribution like this (with sever peaks)

The peaks positions  are different for each channel of the ADC. 

If i repeat this test enabling the digital ramp generator (and not sampling the analog signal) in the test pattern i got a pure white spectrum.

It look like that the INL of the ADC create these peaks but the effect seams to me too big to be acceptable; it is about the 15-20% of counts difference between baseline and peaks.

I investigated the signal shape. I sampled a ramp perdiod that swipe between 0 and full scale. I applied a moving average to reduce the noise (first plot) and calculated the first derivative (second plot) and its filtered version (red in second plot) and i see that the derivate is not linear, There are some humps and each one correspond to a peak in the histogram

Is this the normal behavior of this ADC or we should investigate for any problem on our board? 

is there any way to reduce this effect? (hardware dithering is not possible)

Thank you 

Andrea Abba

  • Hi,

    Thanks for reaching out to us.. I am working on this. Discussing with design team and will get back to you in day or two.

  • Hi,

    I checked INL of the ADC in datasheet. It is as below. We didnt understand your first plot fully. What is x- and y-axis?

    Based on above plot ADC is supposed to give good performance. Have you, by any way, checked the performance of input ramp signal itself? We suspect input signal itself may have distortion...

    Regards

  • Hi,
    in the first plot you have:
    - y axis number of occurrence of the value on x axes
    - x axis LSB (on 13 bit, last bit discarded)
    The plot is obtained peaking random points of the ADC output while input is sweeping in the full input dynamic. The ADC is driven by an LTC6405 used in single ended to differential configuration
    the second plot has on:
    - y axes the LSB
    - x axes the sample
    the third plot has on:
    - y axes the derivate (x[n] - x[n-1]) of the second plot
    - x axes the sample
    I can't grant that the is really good, but i did the test with two different waveform generator, different model and manufacturer and I got the same result with the peaks in exactly same position so I can exclude that the effect is due to the generator.
    Yesterday I partially find a workaround to the problem, that for my application is good. If i lower the sampling frequency to 20 MHz the problem almost disappear. The signal I'm sampling change every 1 us so 20 MHz is more than enough for me. I was using 80 MHz to average the signal and reduce the noise. 
    The fact that the effect is related to the sampling frequency, in my opinion, underline that the cause is inside the converter. I also tested 40MHz and the effect is lower than what i see at 80 MHz but much higher in respect of 20 MHz
    Thank You
    Andrea
  • Thanks Andrea... So I assume as of now you have found the solution to work with.

    One reason we could think of this behavior and clock sensitivity might be related to the ADC driver. Looks like driver capacity is not enough therefore when clock frequency is reduced there is enough time to settle down the sampling network and issue resolves. In future if you want to go to higher sampling speed support, you can look for better driver and sampling glitch filter at the input.