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Original question:

ADS124S08: Programable delay

ADS124S08: Waiting time of the Mux(channel switch)

Wendy Wang1
Genius 16840 points
Part Number: ADS124S08
Other Parts Discussed in Thread: ADS1248

Hi team,

ADS1248 datasheet clearly states that when a channel is saturated with output and this channel is switched to another channel, the switch will not take effect immediately, and a certain waiting time will be required. However, there is no description related to this in the device'ADS124S08'. Can it be understood as: For the device'ADS124S08', even if one channel is saturated with output and it is switched to another channel, switching can be effective immediately without any waiting time? 

Thanks a lot for your kindly help!

Best regards,

Wendy

  • +1
    TI__Guru** 113765 points

    Hi Wendy,

    The ADS1248 was designed quite a number of years prior to the ADS124S08.  There were a number of features and enhancement made to the ADS124S08 that are not available on the ADS1248.  One of the features is a PGA rail flag in the Status register that will indicate if a PGA overload has taken place.  Another feature is the Programmable Conversion Delay in the PGA register.  The delay serves two purposes.  The first is an added delay before starting a conversion following a mux change.  The default setting is 14 tmod periods of delay (which is approximately 54.7us).  The delay setting can be reduced to 1 tmod period or increased to as much as 4096 tmod periods (16ms).  Lengthening the delay will provide the second use case where analog settling is taking place on the analog inputs and increased delay before start of conversion can be added to allow the settling to complete.  This can be useful when multiple RTDs are connected to the ADS124S08 and IDACs are being switched between input measurements.  The overall benefit is the delay can be added automatically and does not require extra processing by the micro.

    In the case of the ADS1248, the mux change will happen within a 2 tmod period from the falling edge of the the last bit of the mux write, but will not have the assigned delay period following the mux change for the conversion to start.  If the PGA was in either an overload condition, or the mux change causes an overload condition of the PGA, then additional time from the processor requires a delay to restart the conversion or to wait for the conversion to complete and discard the first conversion.  This is not necessary with the ADS124S08 as the device has a built in delay.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    TI__Genius 16840 points

    Hi Bob,

    Thanks a lot for the detailed description. It helps a lot!

    I still have one question regarding to this overload case. If overload happens(voltage applied to the input pins of the ADS124S08 is too large to make the PGA saturated), and then overload is removed(voltage applied to the input pins of the become normal), then how long is needed to wait for the PGA to output the right value. This is important to determine how much delay we need to start the ADC conversion after the input to ADC pins become normal.

    Really appreciate your help!

    Best regards,

    Wendy

  • 0 in reply to Wendy Wang1
    TI__Guru** 113765 points

    Hi Wendy,

    That is a very good question and the best answer I can give is to monitor the PGA status bits.  The overload will clear quickly but the residual effects will depend greatly on data rate and digital filter setting.  So at 4ksps, you may need several conversion cycles for the overload to normalize, but at 20sps the effects of the overload may not be apparent as the overload will average out over time.  So unfortunately there is no clear delay time to give you that would cover all settings for the device.  This will be dependent on the system and configuration of the device.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    TI__Genius 16840 points

    Hi Bob，

    Thanks a lot!

    According to our understanding, the stabilization time of the PGA(follow the right input) is the key point. The digital filter afterwards is not that critical, sine we only start the conversion(low latency, single shot) after we are sure that the PGA output is correct.

    And also, the PGA status is not that useful, since it only indicate that the PGA is not saturated, and it doesn’t mean the output is already correct(follow the input). So, the critical information is the how long the PGA is needed to recover from saturated state to correctly follow the input(input from high to normal). Then we can wait that time to start the ADC conversion accordingly.

    Really appreciate your help!

    Best regards,

    Wendy

  • +1 in reply to Wendy Wang1
    TI__Guru** 113765 points

    Hi Wendy,

    One of the reasons the Status register was included to the ADS124S08 was for monitoring the PGA output with comparators (see datasheet Figure 77).  There is no other way to monitor to see if a PGA overload condition exists as there are no probe points where this overload can be measured.  Unfortunately if you are using single-shot mode, the PGA flags are not set if the ADC is not converting.

    If there is a PGA overload condition still taking place after the conversion is started, the rail flag will be set and will be indicated in the PGA flags in the Status register (or transmitted in the Status byte).  In this way it can be determined that there is an overload condition still present and another conversion should be made on the input channel.  In a similar way, if there was a previous channel PGA overload condition, and the mux is switched and the conversion is started, then if the PGA status bits are clear the conversion is now valid.

    By default, there is an approximate 55us delay following the START command to allow for settling.  So there are already built in delays for these kind of issues.

    Best regards,

    Bob B