Data converters forum - Recent Threads

ADC124S021: Maximum delay from /CS falling edge to first SCLK and intermittent abnormal output codes

Ryu Yamashita — Fri, 03 Jul 2026 13:06:41 GMT

Part Number: ADC124S021

Hi team,

Since I have not received a reply, I am reposting this.

Background: We are using ADC124S021CIMMX to measure a thermocouple-related signal on IN4. The analog input voltage appears stable, but the ADC output code intermittently changes abnormally. In our current timing, /CS is driven low and the SCLK burst starts approximately 4 ms later. The burst contains 16 SCLK cycles.

Questions:

Is there any maximum allowed delay from /CS falling edge to the first SCLK edge when /CS is held low?
If /CS is held low for several milliseconds before the 16-clock burst, can SCLK glitches or missed edges cause the internal serial state to shift without automatic timeout recovery?
Does TI recommend toggling /CS high after every 16-clock frame to re-synchronize the interface for this device?

Best Regards,
Ryu.

AFE4490SPO2EVM: Need Altium designer files for AFE4490SPO2EVM

Sunil Tank — Fri, 03 Jul 2026 11:06:30 GMT

Part Number: AFE4490SPO2EVM

Hello,

We urgently required hardware design files of AFE4490SPO2EVM for Altium or any other designer tool .

It will be great help if you provide that.

Thanks for your support.

ADS112C04: Pull Up DRDY# Pin with 1.8V

Ramakrishna Raja C — Fri, 03 Jul 2026 10:04:22 GMT

Part Number: ADS112C04

Hi Team,

Can I Pull up DRDY# Pin with 1.8V Since my SoC GPIO operates at 1.8V

ADC Datasheet says: Data ready, active low. Connect to DVDD using a pullup resistor.
My ADC DVDD is 3.3V

Kindly confirm DRDY is Open drain and can be pulled to 1.8V operates without any issue.

DAC80501: DAC80501MDQFT Output Range

Eli Hait54 — Fri, 03 Jul 2026 09:29:25 GMT

Part Number: DAC80501

Hi,

If the VDD=5V and using internal Vref with REF-DIV=0 and BUFF-GAIN=1, what will the maximum VOUT range (it will be less than VDD, right?)?

Thanx,
Eli.

ADC12DJ5200RFEVM: TI JESD204C IP support on Versal VCK190 with ADC12DJ5200RFEVM

hiroyuki.tanaka — Fri, 03 Jul 2026 08:40:22 GMT

Part Number: ADC12DJ5200RFEVM

Is the TI JESD204C IP supported on Versal VCK190?

We would like to evaluate the ADC12DJ5200RFEVM using the TI JESD204C IP (TI204C-IP v1.12) on a Versal VCK190.

Would it be possible to receive a reference design for the VCK190?

Our target mode is JMODE46 (single-channel, DDCx4, 8-lane 64b/66b, lane rate 10.725 Gbps, E=1).

DAC8163: Model: DAC8163SDSCR chip burning exception

jack liu — Fri, 03 Jul 2026 07:26:18 GMT

Part Number: DAC8163

Model: DAC8163SDSCR,
When burning, I execute the first instruction first and then the second instruction. No output was found. Applying an external reference and executing the second instruction results in output, which means the internal reference does not work. Please take a look at the reason

The last command is not reflected
Execute the first instruction first, and then execute the second instruction. No output was found. Apply an external reference, then execute the second instruction, and there will be output

ADS8665: ADS8665: AIN_P Voltage When AVDD is Off but DVDD is Present

Jacob — Fri, 03 Jul 2026 07:21:49 GMT

Part Number: ADS8665

Hi TI Experts,

I have a question regarding the ADS8665 input behavior under a specific power condition.

Application Background:
I am using the ADS8665 to measure analog voltages from an external peripheral connected to the AIN_P pin. In my system:

DVDD is supplied by a 3.3V rail.
AVDD is supplied by a separate 5V rail.

The Issue:
I have observed that when the AIN_P pin is left floating (no external peripheral connected), there is a voltage of approximately 1.x V present on the pin. I understand from the datasheet and related E2E discussions that this is due to the device's internal biasing voltage, which is normal and does not indicate a problem.

My Question:

If I turn off AVDD (set to 0V) while DVDD remains at 3.3V, can I guarantee that the AIN_P pin will have no voltage (0V) on it?

Thank you for your support.

Best regards,
Jacob

ADS122S14: Data rate unexpectedly drops/resets to 20 SPS when switching MUX channels in Continuous Conversion Mode

hyung ho bae — Fri, 03 Jul 2026 06:41:19 GMT

Part Number: ADS122S14

Hello,

I am currently working on a project using the ADS122S14 to measure 4 sensor channels (2 Differential and 2 Single-Ended).

I am experiencing an issue where the ADC seems to measure at 20 SPS right after switching channels, even though I configured it for a much higher data rate. My application requires a channel switching and measurement time of less than 2.5 ms per channel, so 20 SPS (~50 ms per sample) is too slow.

[My Configuration & Setup]

ADC: ADS122S14
Inputs: 2 Differential Channels, 2 Single-Ended Channels
Conversion Mode: Continuous Conversion Mode
Filter Settings: OSR = 32, Speed Mode = 3

[The Problem]

I initialize the registers with OSR=32 and Speed Mode=3 to achieve a high data rate.
In Continuous Conversion Mode, whenever I update the MUX register to switch to the next channel, the data conversion rate drops/reverts to 20 SPS.
It takes too long to get the settled data for the new channel.

[Questions]

Why does the data rate drop or default to 20 SPS when the MUX channel is changed? Does changing the MUX register automatically reset the data rate configuration or require a specific register re-write sequence?
To achieve my goal of measuring each channel within 2.5 ms, should I switch to Single-Shot Mode instead of Continuous Conversion Mode? If so, what is the recommended register setting and timing sequence for scanning multiple channels rapidly with OSR=32 / Speed Mode=3?

Any insights or recommended code sequences to resolve this timing issue would be highly appreciated.

[Code]

//init. reg.

uint8_t reset_cmd[2] = {0x84, 0x58};

HAL_GPIO_WritePin(SPI1_CS_GPIO_Port, SPI1_CS_Pin, GPIO_PIN_RESET);

HAL_SPI_Transmit(&hspi1, reset_cmd, 2, 100);

HAL_GPIO_WritePin(SPI1_CS_GPIO_Port, SPI1_CS_Pin, GPIO_PIN_SET);

HAL_Delay(10);

ADS122S14_WriteReg(0x05, 0x03);

delay_us(100);

ADS122S14_WriteReg(0x06, 0x01);

delay_us(100);

ADS122S14_WriteReg(0x07, g_ucMux_Table[0]);

delay_us(100);

ADS122S14_WriteReg(0x08, 0x01);

delay_us(100);

ADS122S14_WriteReg(0x09, 0x04);

delay_us(100);

ADS122S14_WriteReg(0x04, 0x02);

delay_us(100);

Thank you!

RE: AM2434: Flash Booting Multi-Core (AMP) AppImage on am2434-lp

Meet Thakar — Fri, 03 Jul 2026 05:56:39 GMT

[quote userid="706733" url="~/support/data-converters-group/data-converters/f/data-converters-forum/1660431/am2434-flash-booting-multi-core-amp-appimage-on-am2434-lp/6403113"]Thank you. I have gone through this process and have been able to successfully generate the signed multicore image. However, I am trying to flash this QSPI flash and within "default_sbl_opsi.cfg" it requires a "_xip" version of the file. How would I go about generating a "_xip" version of my "final_multicore.appimage.hs_fs"? Is the "_xip" not required?[/quote]

If you don't have any requirements to enable XiP for your application then you don't need to flash the _xip binary, you can just remove that line from .cfg file.

You can refer to any makefile in the SDK for this: https://github.com/TexasInstruments/mcupsdk-core/blob/next/examples/drivers/ipc/ipc_rpmsg_echo/am64x-evm/system_freertos_nortos/makefile#L118

PRU Firmware is not usually loaded by the SBL and are not a part of the multicore appimage, we have some APIs that you can use from your R5 Application to load the firmware on PRU cores, please refer to this: https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/12_00_00_26/exports/docs/api_guide_am243x/COMPONENT_PRU_GUIDE_PROG.html

You can also refer to this example: https://github.com/TexasInstruments/mcupsdk-core/blob/next/examples/pru_io/empty/am243x-evm/r5fss0-0_freertos/main.c

AM2434: Flash Booting Multi-Core (AMP) AppImage on am2434-lp

Daniil Nahliuk — Wed, 01 Jul 2026 21:13:26 GMT

Part Number: AM2434

SK-AM62: Flash Booting Multi-Core (AMP) AppImage (a53ss0-0, a53ss0-1) on FreeRTOS - Processors forum - Processors - TI E2E support forums

Tried following this thread for multi-core image creation. I was able to generate a single image and a _xip version of it using genimage.py but after trying to flash QSPI flash using uart_uniflash.py an error occured right after the sent of .mcelf_xip file.

The error message:
"[STATUS] ERROR: Flashing failed !!!"

two files I am trying to flash to the QSPI flash of am2434-lp are:
1. multi-core-image.mcelf
2. multi-core-image.mcelf_xip

When following that thread the signing of the multi-core image was discussed but withing my sdk:
mcu_plus_sdk_am243x_11_02_00_24 --- the appimage_x509_cert_gen.py does not exist

I have looked through the SDK documentation and it does mention the x509 signing but there are not .py files to do that within my sdk as I mentioned.

From this I have these questions:
1. What is the correct procedure to generating multi-core image files on am2434-lp and then flashing them to QSPI?
2. Is the signing step using appimage_x509_cert_gen.py necessary for this board? If yes where can I access one that will work with am2434-lp?

ADS8326: Regarding DCLOCK issue

Daisuke Higa — Fri, 03 Jul 2026 04:32:45 GMT

Part Number: ADS8326

Hi support team all.

I received argent inquiries from our customer in the following.

Could you confirm regarding these inquiries?

1. Potential risk of exceeding the specified limit (6 MHz input)

If a 6 MHz DCLK exceeding the specified limit (4.8 MHz) is input in a VDD=3.3 V environment, is there a risk of any defects (Missing data, loss of accuracy, etc.) occurring in the internal operation of the ADC?

Also, is there a risk that such defects will become apparent in the future due to changes in environmental temperature or the lapse of operating time?

2. Risk of IC failure If operation with a clock exceeding the timing specification is continued, is there a risk that the internal of the IC will deteriorate and Is there a risk that it will eventually break down?

Best regards,

F29H859TU-Q1: Why VREFHI is 0.65V?

ken sugito — Wed, 01 Jul 2026 02:10:38 GMT

Part Number: F29H859TU-Q1

The internal voltage reference range for ADC C, ADC D, and ADC E is described as 0 V to 3.3 V.

However, the VREFHI voltage observed at the DSP pin is 0.65 V rather than 3.3 V.

We believe that the reason VREFHI at the DSP pin is 0.65 V is that this voltage corresponds to the REF terminal voltage of the internal shunt regulator. Is our understanding correct?

RE: F29H859TU-Q1: Why VREFHI is 0.65V?

ken sugito — Thu, 02 Jul 2026 23:50:28 GMT

Hi Joseph,

Thank you for your response.

I see, so a bandgap reference circuit is being used.

Understood.

Regards,

Ken

RE: F29H859TU-Q1: Effect of ADC Input on VREFHIAB and VREFLOAB

ken sugito — Thu, 02 Jul 2026 23:47:13 GMT

Hi Joseph Casuga,

Thank you for your response.

The package type is QFP.

Thanks,

Ken

F29H859TU-Q1: Effect of ADC Input on VREFHIAB and VREFLOAB

ken sugito — Wed, 01 Jul 2026 01:49:59 GMT

Part Number: F29H859TU-Q1

We are using ADC-A only as an A/D converter and not as a comparator input.

In our development unit, a high-frequency signal is present on the ADC-A A1 input.

When the level of this high-frequency signal increases, the measured values of other ADC channels monitored by ADC-A also change.

We suspect that the internal DSP routing/pattern for either VREFHIAB or VREFLOAB may be located close to the ADC-A input routing/pattern, causing coupling between the signals.

Could this be the case?

We would appreciate your comments on this possibility.

ADS7038-Q1: Clarification of behavior of opcodes on the SYSTEM_STATUS Register

Jeremy Barney — Thu, 02 Jul 2026 21:57:31 GMT

Part Number: ADS7038-Q1

THE SYSTEM_STATUS OSR_DONE, CRCERR_IN, and BOR bits each have a description that includes the following phrase: "Clear this bit by writing 1b to this bit," or "Write 1b to clear this error flag," or "Write 1b to this bit to clear the flag."

I am hoping to get clarification for each of the opcodes. For this example, I want to clear the OSR_DONE bit and it is already set to 1.

First, the SET_BIT opcode: if I set the mask to 8'b00001000, will this actually clear the OSR_DONE bit, or will it leave it as 1?

Second, the CLEAR_BIT opcode: if I set the mask to 8'b00001000, will it clear the OSR_DONE bit as expected?

Third, the SINGLE_REGISTER_WRITE opcode: if I set the mask to 8'b00001000, will it clear the OSR_DONE bit or keep it set? Conversely, if I set the mask to 8'b00000000, will it clear the OSR_DONE bit or keep it set?

I am asking because the read/write bits in the SYSTEM_STATUS register and the EVENT flag registers are the only registers that have the language of "write 1b to clear." But this behavior would seem to conflict with the normal semantics of the SET_BIT and the SINGLE_REGISTER_WRITE commands.

DDS39RFS12: Use DDS39RF10/12 without JESD

David Schick — Thu, 02 Jul 2026 19:08:51 GMT

Part Number: DDS39RFS12

I would like to evaluate using the DDS39RF10 or DDS39RF12 parts without a JESD204 input present, and simply use SYSREF and SPI to make them programmable tone generators. The older DAC38 family clearly spelled out the "SPI Constant" feature to enable this in the datasheet.
Does similar functionality exist in the DDS39RF10/12, such that if you supply clock, SYSREF and SPI programming you could transmit multiple tones that are phase-aligned with the SYSREF pulse?

ADS1235: temperature compensation issues

Matthew Love — Fri, 26 Jun 2026 14:48:11 GMT

Part Number: ADS1235

I am currently looking to replace an EOL ADC (Cirrus CS5532) with a similar 24-bit device. We have used many tens of thousands of the CS5532 without tempco issues. I have developed a replacement prototype (photo above) with the ADS1235 and adapted the SPI code of the EFM8 microcontroller. I have configured 3 of the prototypes and compared them with 3 of the previous CS5532 equipped boards. One of the prototypes provides excitation volts (4.6v) to my precision load cell simulator external to the temperature chamber. Sense and signal returns from the simulator are commoned to all 6 modules (but not excitation, of course). Picture above – the switch is to select the TTL232 serial outputs of the six modules.

The precision simulator provides 0.7mV/V at span and 0 at zero. I have calibrated all modules to output 10000.0g at 0.7mV/V, 0.0g at 0mV/V.

Setup params - 50sps, DCexc, continuous, sinc3, PGA x64, AIN4/5 signal in, REFP0/REFN0.

OFCAL: 00,00,00h (approx), FSCAL: 8D,F6,80h (typ).

The analogue schematic is attached.

I have used the previous, quite high input and ref series resistors (22k), so when I encountered issues, I reverted to the application note recommended of 100R and 10nF and 1nF caps (C0G).

This made absolutely no difference.

Over the course of a day, with temperatures varying by no more than 5C (22 to 27C), the ADS1235 zero corrected span creeps up and down typically from 10006.4g to 10027.0g (~200ppm), whilst zero moves 0.0g to 3.8g (38ppm). The weird thing is, all of the ADS1235s seem to track this gain creep. In addition, the low frequency gain variation (1 to 0.1Hz) is much noticeably worse than the CS5532 – about 10 times.

For comparison, the CS5532 results are 10000.0g to 10000.8g (8ppm) and 0.0g to 3.3g (33ppm).

I haven’t yet made it to doing proper temperature testing, as the static results are so poor.

It does seem to have the hallmarks of a silicon problem.

My first thought was, could we have purchased counterfeit devices, but our buyer assures me they as ‘best quality’ from Mouser.

I have attached a picture. The device ID reads back C1h.

RE: ADS1235: temperature compensation issues

Matthew Love — Thu, 02 Jul 2026 15:03:54 GMT

Hi Bryan,

Thanks for your info... here are the replies from the HW team.

I have not tried your EVM module.
An FSCAL value of 8D,F6,80h is not a negative value, in my understanding (gain is unsigned). Unity gain is 40,00,00h, so I’m asking for a gain of just over x2. Or have I totally misunderstood the datasheet?
By “DCexc”, I mean I’ m not using the chop mode. Just 4.6v DC excitation.
Global chop, if I understand correctly, is only going to remove offset drifts.
My processor is taking 20ms samples from the ADS1235, feeding them into a digital filter (IIR) and outputting serial strings 0.7mv/v (approx. 3.2mv absolute) as 100,000d and 0 in as 0 out at 0.3s intervals.
I use a split groundplane, segregated under the ADC to correspond with the digital and analogue pins, with a single link between the two. 5v power crosses the gap above that link, so no circulating currents.

Regards Matt

RE: AM2434: Flash Booting Multi-Core (AMP) AppImage on am2434-lp

Daniil Nahliuk — Thu, 02 Jul 2026 14:56:26 GMT

Also, in the context of am243x what are the CORE IDS for the PRUs cores and in context of am64x CORE IDS for the A53 cores? The SDK documentation only provides IDs for R5 and M4.

RE: ADS1675: Questions about the reference Riso + DFB buffer circuit in ADS1675REF board

ruiming li — Thu, 02 Jul 2026 14:47:12 GMT

Hello Keith,

Thank you for the documentation and circuit design, these really solved my problem. Thank you!

Regards,

Lee

ADS1675: Questions about the reference Riso + DFB buffer circuit in ADS1675REF board

ruiming li — Tue, 30 Jun 2026 17:42:08 GMT

Part Number: ADS1675

Hi team,

In the ADS1675REF board reference Riso + DFB buffer circuit, the Riso(R25) is 100ohm, Rf(R22) is 49.9ohm, Cf(C22) is 0.15uF, this is very different from the design method of the precision labs video course (www.ti.com/.../ti-precision-labs-op-amps.html). In Precision labs series: Op amps - Stability - Isolation resistor : "RISO is selected to produce a zero in the AOL curve at the frequency where the AOL equals 20 dB. Then RF can be selected to any value greater than 100 times RISO in order to prevent interactions with RISO. The last step is to select a value of CF based on the range shown here. Using this range ensures that the two feedback paths never create a resonance that would cause instability."

The 100ohm Riso and 10uF capacitor load generate a zero point at only about 160Hz. I simulated this circuit, it has about 50 degree phase margin at about 7.5MHz, which is before the 0dB crossover.

So is this an optimal design that has been proven in reality? Will not has problems such as interference and resonance mentioned in the video course above.

Thanks,

Lee

RE: AM2434: Flash Booting Multi-Core (AMP) AppImage on am2434-lp

Daniil Nahliuk — Thu, 02 Jul 2026 14:44:46 GMT

Thank you. I have gone through this process and have been able to successfully generate the signed multicore image. However, I am trying to flash this QSPI flash and within "default_sbl_opsi.cfg" it requires a "_xip" version of the file. How would I go about generating a "_xip" version of my "final_multicore.appimage.hs_fs"? Is the "_xip" not required?

ADS9324: Request for Functional Safety Manual and Secure Resources for ADS9324C

Jihae Eom — Mon, 22 Jun 2026 01:59:27 GMT

Part Number: ADS9324C

Hello,

We are currently developing a lead-acid battery monitoring system for industrial UPS and rectifier applications.

This device is being reviewed as a common component for both of the following architectures:

1. 2V 16-channel lead-acid battery cell monitoring system
2. 12V 16-channel lead-acid battery block monitoring system

In our system, this device may be used together with battery monitoring ICs, ADCs, MCUs, and a higher-level BMU controller to support real-time monitoring, protection, diagnostics, and preventive maintenance functions.

Could you please provide access to the available secure resources for this device, including the Functional Safety Manual, Safety Analysis Report, FMEDA, diagnostic documentation, diagnostic libraries, example code, and any other related functional safety or diagnostic materials?

These documents are needed to evaluate the device’s diagnostic coverage, failure detection mechanisms, protection functions, and suitability for our lead-acid battery monitoring system design.

Best regards,
Jung Deuk-keun
President / TwinRISLab Inc.

RE: ADS9324: Request for Functional Safety Manual and Secure Resources for ADS9324C

Josh Brown — Thu, 02 Jul 2026 14:18:33 GMT

Hello Jihae,

Yes! the ADS9324C can be purchased directly from ti.com. We have about 450 units in stock on the website as of right now. I am unable to guarantee that we will have stock in August, but we are planning to build more units and restock the store a few times before the full release of the device.

Regards,
Josh