Data converters forum - Recent Threads

RE: ADS9219EVM: ADS9219EVM Unable to Configure ADC Using TSWDC155EVM and GUI Software

Gopal Krishna — Wed, 04 Nov 2026 08:09:23 GMT

I am unable to update the TSWDC155EVM USB driver through Device Manager. Could you please provide the correct driver and guide me through the installation process?

AFE5932EVM: Wearable ultrasound evaluation board

Celsium — Wed, 04 Nov 2026 07:49:20 GMT

Part Number: AFE5932EVM

Hello TI, we want to conduct experiment described in this post: https://www.nature.com/articles/s41467-025-66001-6

For that we need an evaluation board. We need single-element transmission, 32 simultaneous receivers, automated cycling through TX elements, and raw-channel file export. We will create a 3D printed bracelet with 32 single transducers in it and need to connect them to the evaluation board.

We do not require beamforming, live imaging, GPU integration or continuous high-bandwidth streaming.

Please advise the evaluation board and extra hardware if required for this work.

RE: AMC1303M0520: Abnormal current offset

SHIH HAN CHEN — Wed, 04 Nov 2026 06:02:53 GMT

We have conducted A-B-A testing and confirmed that the anomaly follows the AMC1303, which rules out any hardware issues with the circuit board. 
We have also requested a Failure Analysis (CPR No.CPR261158729 ) through our distributor ARROW, 
however, the TI manufacturer requires that we first consult the E2E forum. 
We are now requesting to send the anomalous component back to the manufacturer for analysis.

AMC1303M0520: Abnormal current offset

SHIH HAN CHEN — Mon, 02 Nov 2026 05:40:34 GMT

Part Number: AMC1303M0520

Anomaly: With no load current flowing through the shunt, the current feedback exhibits a significant offset, which differs notably from the other phases.

Measurement Results: phase offset: 160 mA ,This phase offset is significantly higher than that of the other channels.

System Information:

1. MCU: TMS320F28379D

2. Current Feedback: AMC1303M0520 SDFM

3. SDFM Filter: Sinc3, OSR equal 64

4. Shunt Resistors: 0.001 ohm and 0.0015 ohm in parallel ,equivalent to 0.6m ohm

5. Application: AC Servo Drive

Confirmed Points:

1. Offset calibration procedure is functioning correctly.

2. MCU firmware versions are consistent.

3. SDFM settings are consistent.

4. PCB layout and BOM match the design specifications.

5. The anomaly follows the specific AMC1303 unit.

6. This phenomenon is not observed in units that function correctly.

Items for Further Investigation or Verification:

1. Whether the AMC1303 input offset voltage exceeds the specified range.

2. Whether there is an abnormal offset within the Delta-Sigma modulator.

3. Whether there is internal damage to the component or a drift in its parameters.

UCC34141-Q1: RoHS Compliance Status of TEXAS INSTRUMENTS p/n PUCC34141QDHARQ1

gunjan shrivastav — Wed, 04 Nov 2026 05:07:23 GMT

Part Number: UCC34141-Q1

Hi,

Greetings from Keysight Technologies!!
We would like to seek your help in getting RoHS compliance status of your product mentioned below as per EU Directive 2015/863.

PUCC34141QDHARQ1

TEXAS INSTRUMENTS

RE: UCC34141-Q1: RoHS Compliance Status of TEXAS INSTRUMENTS p/n PUCC34141QDHARQ1

Shinu.V.Mathew — Wed, 04 Nov 2026 05:21:38 GMT

Hi Gunjan,

The device Quality, reliability & packaging information are available on below link.

https://www.ti.com/quality-reliability-packaging-download/report?opn=UCC34141DDHAR

Thanks.

AMC0306M25: AMC0306 DOUT tH & tD with 20MHz CLK

Shaofeng Luo — Wed, 04 Nov 2026 04:29:20 GMT

Part Number: AMC0306M25

Hi experts

We notice that there are two main difference between AMC0306 and AMC1306, they are DOUT tH(hold time) and tD(delay time). If we use 20MHz CLK for AMC0306, falling-edge sampling on CLK doesn't work, because tDmax=30ns, which is longer than 25ns(half clock cycle).

So for AMC0306 working at 20MHz, only rising-edge sampling is acceptable, right?

ADS131M08: Request for Metrology IC Recommendation: 3-Phase 4-Wire Class 0.5S Energy Meter with Leakage and Neutral-Fail Detection

tech iot — Fri, 16 Oct 2026 08:35:32 GMT

Part Number: ADS131M08

Hello,

We are developing a 3-phase 4-wire energy meter and would like your recommendation for a suitable metrology IC, along with any reference design or application support you can offer.
A one-page block diagram and requirements summary is attached.

PROJECT SUMMARY
- 3-phase 4-wire, 3 x 230 V, 50 Hz
- In = 50 A, Imax = 60 A (typical load 30-40 A)
- Accuracy class: 0.5S
- Current sensing: CT-based (preferred), open to a shunt option

IC REQUIREMENTS
1. 3 voltage + 4 current channels, with simultaneous sampling and high-resolution ADCs.
2. Accurate measurement of power, energy, voltage, current, PF, frequency and V-V / V-I phase angles, stable over temperature.
3. Access to raw waveform data, and on-chip gain, phase and offset calibration with temperature compensation.
4. Voltage input range up to about 440 V phase-neutral, to cover neutral-loss conditions.
5. An extra high-resolution current channel (a 5th IC input, or a companion ADC you recommend), time-synchronised with the voltage channels. We will use it with a zero-sequence CT to detect leakage of a few mA and to identify the leaking phase from the residual current angle.

WHAT WE WOULD LIKE FROM YOU
1. Recommended IC part numbers for this meter, and how to add the extra leakage channel with your parts.
2. Class 0.5S test data and calibration guidance.
3. Reference designs, application notes and an evaluation board.

Thank you for your time and support.

RE: ADS131M08: Request for Metrology IC Recommendation: 3-Phase 4-Wire Class 0.5S Energy Meter with Leakage and Neutral-Fail Detection

tech iot — Wed, 04 Nov 2026 04:16:49 GMT

We will used for industrial power management, and street light system, when there is earthing in system, we have to shutdown all 3 phases, but in actual faults in one of the phase, so it disturb whole system rather than specific phase, as shutdown system causes huge loss, so we are trying to find solution, in which system can decide which phase has fault and shutdown that phase only. So in street light only some poles light off, and other works, same in industrial power management.

Please help us to find solution for this problem.

RE: TXS0102: TXS0102DCUR chang the marking from "FDNZ" to "35ST" causes abnormal output signals.

Kevin Huang8 — Wed, 04 Nov 2026 04:12:00 GMT

Hi Joshua,

(1) Could you share the waveform we should be expecting which has the good unit (FDNZ)?

OK waveform / Normal waveform

(2) What is the status of OE pin when TXS powers up?

Response: As shown in the image above.

(

(3) Could we capture VCCA, VCCB, OE and A1 for both FDNZ and 35ST to see if this is a power-up sequence issue.

Fail waveform / Abnormal waveform

After pressing the switch, abnormal oscillation occurs in the waveform roughly 455 ms after VCCB ramps up.

mal oscillation waveform.

(4) What is the trace length from the driver to the TXS inputs and TXS outputs to the receiver?

GP_B16: 2091.7286 mil (CPU side)
GP_B16_5: 732.6723 mil (I/O side)

TXS0102: TXS0102DCUR chang the marking from "FDNZ" to "35ST" causes abnormal output signals.

Kevin Huang8 — Fri, 30 Oct 2026 15:56:56 GMT

Part Number: TXS0102

Component Change Issue: We changed the component marking from "FDNZ" to "35ST". After this change, 3 out of 3 sample pieces failed the customer's inspection.
Failure Trigger: The issue happens immediately at power-on when the switch is pressed.

CPU side

Via Level shift

Board Connector to Power Switch

Waveform Query:

Pin_05

Pin_08

ADS1278: ADS1278 AGND/DGND Connection for Split Analog and Digital Ground Planes

KEIZO MIZUI — Mon, 02 Nov 2026 06:32:42 GMT

Part Number: ADS1278

Dear TI Support,

The ADS1278 datasheet states:

"Analog ground; connect to DGND using a single plane."

I understand that the AGND and DGND pins of the ADS1278 should be connected to the same ground plane.

However, our PCB has separate analog and digital ground planes , which are connected at a single point near the power connector.

Does "using a single plane" mean that the entire PCB should use a common ground plane?

Or is it acceptable to keep the analog and digital ground planes separate and connect them at a single point?

Could you please advise on the recommended ground layout?

Best regards,

RE: ADS1278: ADS1278 AGND/DGND Connection for Split Analog and Digital Ground Planes

KEIZO MIZUI — Wed, 04 Nov 2026 00:51:07 GMT

Dear Keith Nicholas

Thank you for your detailed explanation.

I had thought that separating analog and digital ground planes was generally the preferred approach.

I now understand that, in many cases, using a single solid ground plane while keeping analog and digital components and signal traces physically separate is a better approach.

Your explanation, including the example of the ADS1278EVM, was very helpful.

Thank you again for your support.

Best regards,
Keizo Mizui

ADS8332EVMV2-PDK: ADS8332EVMV2-PDK: PHI controller communication protocol / using EVM without PHI

Beomsu Ryu — Tue, 03 Nov 2026 08:17:19 GMT

Part Number: ADS8332EVMV2-PDK

Hello,

I am evaluating the ADS8332 with the ADS8332EVMV2-PDK (user’s guide SBAU251B).

Is there any documentation of the communication protocol between the PC and the PHI controller (USB side), or an API/DLL that we could use from our own software instead of the LabVIEW GUI?
If not, we plan to drive the ADS8332EVMV2 directly from our own MCU through connector J2 (SPI + 5.5 V / 3.3 V supplies). Are there any precautions, such as power sequencing, the EEPROM (U10), or the jumper settings, that we should be aware of?

Product information (from the package label):
- Part number: ADS8332EVMV2-PDK
- Date code: 2352
- Lot: 3015155KRY

Thank you.

RE: ADS8332EVMV2-PDK: ADS8332EVMV2-PDK: PHI controller communication protocol / using EVM without PHI

Beomsu Ryu — Wed, 04 Nov 2026 00:00:09 GMT

Hi Rahul,

Thank you for the quick and clear answer.

Understood that there is no API for the EVM-PDK outside the GUI. I have a few follow-up questions:

1. USB protocol
Could TI share the USB communication protocol between the host PC and the PHI controller (e.g., VID/PID, driver type, and the command/packet format for register read/write and data capture)? With this, we could implement the communication ourselves in our Visual C++ application while keeping the existing PHI + ADS8332EVM hardware.

2. Recommended MCU board
If the protocol cannot be shared, we will proceed with direct MCU control of the ADC card as you suggested. Could you recommend a TI MCU board (e.g., a LaunchPad) that is well suited for interfacing with the ADS8332EVM? It would be helpful if the board supports the required SPI speed for the ADS8332's full sample rate and can transfer data to a PC over USB. Any available example code or reference design for ADS8332 + MCU would also be appreciated.

ADS1299: ADS1299: START Pin Sampling Edge Relative to Master Clock (fCLK) and Multi-Device Synchronization

longfei zhang — Sun, 01 Nov 2026 03:34:56 GMT

Part Number: ADS1299

Dear TI Engineering Team,

We are developing a 32-channel EEG acquisition system using four ADS1299 devices.

The four ADS1299 devices share the same external 2.048 MHz master clock (fCLK), a common START signal, and identical data rate and register configurations.

Each ADS1299 has an independent DRDY signal connected to a MCU. The MCU reads the four devices sequentially through a shared SPI bus.

We would like to clarify the internal timing mechanism of the START input.

Is the START pin internally synchronized to the master clock (fCLK)?
Is the START input sampled on the rising edge or falling edge of fCLK?
What are the required setup and hold times of the START input relative to fCLK?
When four ADS1299 devices share the same fCLK and START signals, are all four devices guaranteed to start their conversions on the same fCLK cycle?
What is the maximum timing skew between the conversion start times or DRDY falling edges of multiple ADS1299 devices under identical clock and START conditions?

Our design target is to keep the inter-device sampling time skew below 1 microsecond.

We would appreciate clarification of the internal START synchronization mechanism and any relevant timing specifications not explicitly specified in the ADS1299 datasheet (SBAS499C).

Thank you for your technical support.

RE: ADS1299: ADS1299: START Pin Sampling Edge Relative to Master Clock (fCLK) and Multi-Device Synchronization

Ryan Andrews — Tue, 03 Nov 2026 22:34:36 GMT

Hi Longfei,

Thank you for your post.

It's unclear whether the START pin needs to be held high for two consecutive CLK rising edges, or if it is simply latched on the CLK falling edge (see Figure 69). We do not have setup/hold times specified for the START pin, but I would assume it is close to the same requirement as given for the serial interface (i.e., 10ns minimum for setup/hold times).

How much control do you have in bringing the START pin high with respect to the CLK rising/falling edges?

I would suggest bringing the START pin high at least 10ns before the CLK rising edge and to hold it high for two CLK periods as mentioned in the datasheet. This would ensure that all devices latch the START signal on the same CLK edge (either the 1st/2nd rising edge or the 1st falling edge) and synchronize the respective /DRDY interrupts to the same CLK period. You can also validate this on an oscilloscope after pulsing the START pin high. Since the CLK period is about 488ns, the /DRDY interrupts should be synchronized to the same CLK edge or at most 488ns apart.

Regards,

Ryan

RE: DS90UB954-Q1: Converting MIPI-CSI to DSI

Caitlin Behne — Tue, 03 Nov 2026 20:56:08 GMT

Hello Neta,

A few more follow-up questions before I give an SoC recommendation:

What are the resolution, frame rate, and color depth requirements for the display?
Is there a specific power budget for the bridge/SoC portion, or a general target?
How many DLPC8424 ports are in use?
You mentioned "DLPC8424 or alternative", are there specific alternative controllers under consideration?
Is there a cost or board space constraint on adding an SoC to the design?

Also, yes, the DS90UB953/954 pair does consume meaningfully less power than DS90UB947/948. Combined, it's roughly 730mW typical / 969mW max for the 953/954 pair vs. roughly 1317mW typical / 1830mW max for the 947/948 pair. Note this covers only the FPD-Link portion, the SoC itself will add its own power draw, which may be significant depending on the part selected.

I will follow up once I have answers.

Best regards,
Caitlin Behne

DS90UB954-Q1: Converting MIPI-CSI to DSI

Neta Sherer — Sun, 01 Nov 2026 19:17:11 GMT

Part Number: DS90UB954-Q1

Hi,

We are building an application where we would like to use the following arhitecture.

In that case, we would like to know the following:

Is there any FPDLink3 pair which supports DSI to DSI interface (other than MIPI).
If not, what can be a good candidate for MIPI to DSI data converter?

Please advice,

DAC43701: Schematic Review

Allan Fan — Thu, 29 Oct 2026 08:59:58 GMT

Part Number: DAC43701

Hi experts,

Would you please support to review the schematic of DAC43701? It's used to output adjustable Vref for comparator TLV3601 for core power(0.65/0.75/0.85V) monitoring.

Thanks,

Allan

RE: DAC43701: Schematic Review

James Steenbock — Tue, 03 Nov 2026 20:17:43 GMT

Hi Lihuai,

This schematic looks good now.

Regards,

James

RE: AMC0106M05: Pins 9 and 10 of AMC0106M05 left unconnected. Concerns?

Alexander Smith — Tue, 03 Nov 2026 19:54:36 GMT

Hi Kevin,

I've pasted the below from our AI assistant which I generally agree with. The main purpose of these pads are for thermals. So it depends on what your ambient temperature expectation is and that inside the IC, higher temperatures will be seen than normal and therefor more drift components as well. In general, I would recommend fixing this on the next revision. To check thermals inside you can mark the top of the IC with a sharpie then use a FLIR or other thermal imaging camara to get a feel for the junction temperatures.

Can you share some details on how this IC is being used in your application?

Short answer: your grounds are not floating. Pin 9 (AGND exposed pad) is internally connected to pin 4 (AGND) and pin 10 (DGND exposed pad) to pin 5 (DGND), each through a low-impedance path 1. So long as pins 4 and 5 are properly tied to your AGND and DGND planes, the device will be biased and function normally — the modulator still has valid ground references.

What you lose by not connecting the pads

TI's recommended layout (Figure 7-5, which you attached) connects both exposed pads directly to their respective ground planes for three reasons 1:

Benefit lost	Practical consequence
Thermal dissipation path	Higher junction temperature; package relies on perimeter pins only
Internal shielding	Reduced immunity to common-mode transients and radiated EMI coupling
Low-impedance reference return	Ground reference established only through pins 4/5 and their trace inductance

On noise susceptibility: yes, in principle — the pads provide electrical shielding against high common-mode transients and EMI 1. But the magnitude is layout-dependent and not quantified anywhere in TI's documentation. There is no A/B characterization of connected vs. unconnected pads, so I can't give you an expected mA or ENOB delta. The device's specified 150 V/ns minimum CMTI is characterized with the recommended layout, not without it 2.

Recommended path forward

Test it. Measure RMS noise on your current channel under worst-case PWM switching and compare against the OSR-dependent baseline: 18.4 mA RMS at OSR 32 down to 2.51 mA RMS at OSR 256 (11.1 to 14 bits ENOB) from the reference design 3. If you're close to those numbers, your boards are usable.
Verify your input filter. Since you've given up the pad shielding, the anti-alias filter matters more. Without it, noise near the modulator sampling frequency aliases down into your signal band; mismatched common-mode capacitors also create differential errors during common-mode transients 4.
Check thermals at full load, since the primary heat path is missing.
Fix on next revision — connect pad 9 to the AGND plane and pad 10 to the DGND plane per Figure 7-5.

One clarification worth confirming: are pins 4 and 5 themselves connected to your ground planes? If those are also unconnected, that's a functional problem, not just a performance one.

AMC0106M05: Pins 9 and 10 of AMC0106M05 left unconnected. Concerns?

K-Dog — Tue, 03 Nov 2026 19:40:45 GMT

Part Number: AMC0106M05

Hi TI Team,

We accidently left pins 9 and 10 unconnected in our AMC0106M05 design instead of tying them to AGND and DGND. What impact will this have to our current sensing results? Will the device be more suseptible to noise?

Thanks,

Kevin

ADS8688W: Request for Corrected Datasheet and Technical Confirmation – ADS8688WDBTR

Sandhya G — Fri, 16 Oct 2026 10:46:07 GMT

Part Number: ADS8688W

Dear Texas Instruments Support Team,

During our technical validation of MPN ADS8688WDBTR, we identified the following documentation discrepancies:

The device comparison table in the datasheet lists ADS8674 and ADS8678, which do not correspond to the requested MPN ADS8688WDBTR.
The packaging information section displays the package and pin details for ADS8688WDBTR as “null (null)”, instead of specifying the applicable package type and pin count.

Kindly confirm the following:

The correct package type and pin count for ADS8688WDBTR

We also request you to provide the latest corrected datasheet for ADS8688WDBTR, including the correct device comparison, package, and pin information.

The relevant screenshots are attached for your reference.

Your clarification and the corrected datasheet will help us complete our internal technical validation.