Data converters forum - Recent Threads

ADS124S08: Offset Calibration at PGA Gain change

Toshiya Asai — Tue, 07 Jul 2026 05:19:31 GMT

Part Number: ADS124S08

Dear Support Team,

I would like to perform the following measurements using the ADS124S08:
Reset -> SFOCAL -> Execute a measurement loop while switching input channels.
Within the measurement loop:
(1) Perform one single-shot read for each channel and immediately switch to the next channel.
(2) Switch the PGA gain when performing the single-shot read. However, I would like to avoid performing SFOCAL here as it would slow things down.
Therefore, as a solution,
(1) At initialization, or at certain time intervals, execute SFOCAL for each gain to be used all at once and record the OFCAL0/1/2 register values.
(2) In the measurement loop, when switching gains, restore the OFCAL0/1/2 values corresponding to that gain and perform a single-shot read.
Is it possible to perform measurements without spending time on SFOCAL during the measurement loop using this process?
Please let me know if you have any prolblems.

Thanks,

Toshiya

RE: ADS124S08: Offset Calibration at PGA Gain change

Toshiya Asai — Wed, 08 Jul 2026 23:43:58 GMT

Hi Dale,

Thanks for your reply,

Just to be sure, let me confirm again.
As indicated in the title, the Gain is also switched when switching channels.
Since the offset shifts when switching Gain, I thought restoring OFCAL0/1/2 would solve the problem.
(Example)
Select Ch1 → Restore OFCAL for Gain_x4 → single-shot read
↓
Select Ch2 → Restore OFCAL for Gain_x32 → single-shot read
↓
Select Ch3 → Restore OFCAL for Gain_x16 → single-shot read
↓
Are there any drawbacks to frequently switching the gain?
Also, as you suggested, correcting it in the firmware using OFCAL is also a good method.
Could you tell me the formula for that correction?

Regards,

Toshiya

RE: ADS1235: temperature compensation issues

Bryan Lizon86 — Wed, 08 Jul 2026 22:43:35 GMT

Hi Matthew Love,

Thanks for getting back to me

Apologies about the confusion on the FSCAL value, agreed that it is something like 2.12. Why not just use the gain of 128 then, and reduce the FSCAL value?

Do you have the capability to try any of the things I suggested e.g. test with our EVM to compare performance against a different layout, enable the global chop mode to see if this makes a difference, etc.? We've never done a direct comparison between the CS5532 and the ADS1235 before, so I am not sure what to expect or how different the measurements should be. Therefore I need your help to try to some tests to see if we can narrow down what the issue is

I can try to run some tests on my end using the EVM, but of course it will be more efficient for you to do so since you can use the same simulator and remove another variable

-Bryan

ADS1235: temperature compensation issues

Matthew Love — Fri, 26 Jun 2026 14:48:11 GMT

Part Number: ADS1235

I am currently looking to replace an EOL ADC (Cirrus CS5532) with a similar 24-bit device. We have used many tens of thousands of the CS5532 without tempco issues. I have developed a replacement prototype (photo above) with the ADS1235 and adapted the SPI code of the EFM8 microcontroller. I have configured 3 of the prototypes and compared them with 3 of the previous CS5532 equipped boards. One of the prototypes provides excitation volts (4.6v) to my precision load cell simulator external to the temperature chamber. Sense and signal returns from the simulator are commoned to all 6 modules (but not excitation, of course). Picture above – the switch is to select the TTL232 serial outputs of the six modules.

The precision simulator provides 0.7mV/V at span and 0 at zero. I have calibrated all modules to output 10000.0g at 0.7mV/V, 0.0g at 0mV/V.

Setup params - 50sps, DCexc, continuous, sinc3, PGA x64, AIN4/5 signal in, REFP0/REFN0.

OFCAL: 00,00,00h (approx), FSCAL: 8D,F6,80h (typ).

The analogue schematic is attached.

I have used the previous, quite high input and ref series resistors (22k), so when I encountered issues, I reverted to the application note recommended of 100R and 10nF and 1nF caps (C0G).

This made absolutely no difference.

Over the course of a day, with temperatures varying by no more than 5C (22 to 27C), the ADS1235 zero corrected span creeps up and down typically from 10006.4g to 10027.0g (~200ppm), whilst zero moves 0.0g to 3.8g (38ppm). The weird thing is, all of the ADS1235s seem to track this gain creep. In addition, the low frequency gain variation (1 to 0.1Hz) is much noticeably worse than the CS5532 – about 10 times.

For comparison, the CS5532 results are 10000.0g to 10000.8g (8ppm) and 0.0g to 3.3g (33ppm).

I haven’t yet made it to doing proper temperature testing, as the static results are so poor.

It does seem to have the hallmarks of a silicon problem.

My first thought was, could we have purchased counterfeit devices, but our buyer assures me they as ‘best quality’ from Mouser.

I have attached a picture. The device ID reads back C1h.

RE: ADS124S08: Offset Calibration at PGA Gain change

Dale Li — Wed, 08 Jul 2026 22:39:55 GMT

Hi Toshiya,

Welcome to TI E2E forum.

SFOCAL is a command for self offset calibration, so the offset error is almost the same under the same gain setting on the different channels of the ADC because all input channels use the same PGA and modulator, so you can use the saved OFCAL0/1/2 values for the self offset calibration on other channels, however you have to write the saved OFCAL0/1/2 value into those calibration register before perform a single-shot read or you can use the saved OFCAL0/1/2 value to do an offset calibration in your firmware.

The SYOCAL command is different because the system offset error might be different on individual channels in your circuit, the system offset error on an individual channel includes the error of the front-end circuit.

BR,

Dale

RE: DAC8831EVM: DAC8831EVM GUI cannot connect to the device

Zoe Yang — Wed, 08 Jul 2026 22:06:49 GMT

for (2) I have suspected of this and checked Device Manager

I found 5 devices showing up as I unpluged and repluged the USB

These are "USB Composite Device" that uses a Microsoft driver, and 4 "USB serial converter" that uses FDTI driver. But I am not sure if the FTDI driver is using the correct path.

Is this normal that 4 devices showing up? And are they using the correct driver?

DAC8831EVM: DAC8831EVM GUI cannot connect to the device

Zoe Yang — Tue, 07 Jul 2026 21:08:08 GMT

Part Number: DAC8831EVM

the moment I open GUI this shows up, and does not help by connet/disconnect the USB to the DAC8831EVM again and again

It is possible to go to demo mode

ADS1261EVM: Configuration Input

Giorgio Valente — Tue, 07 Jul 2026 15:22:53 GMT

Part Number: ADS1261EVM

Dear Support,

i would like to use ADS1261-Q1 in my application, but i'd like to test some of its features on ADS1261EVM. In my case i have to read 9 PT100 sensors and i was looking for a possible configuration to do that: i read application note SBAA275A "A basic guide to RTD Measurements" and maybe the most suitable solution would be the one reported here below.

In my understaing, this would lead to multiple ADS1261 to be used, because one ADS1261 could handle just 2 PT100 (for ADS1261 IN0 and IN1 would be configured as REFP0 and REFN0, and the remaining 8 channel must be configured as 2 differential input and 2 IDAC source). I think that it is not so efficient as solution so i was looking for something different: here below i report a possible configuration that i found in topic for ADS1248.

So my questions are:

is ADS1261EVM suitable in order to evaluate all the different configuration i was talking about?
Which configuration is the best for 9 PT100 from your point of view ?
in the configuration from ADS1248 topic, how do you configure input filter?

Thanks in advance for your help.

Kind regards,

Giorgio

RE: ADS1261EVM: Configuration Input

Maggie Lee — Wed, 08 Jul 2026 20:13:18 GMT

Hi Giorgio,

Welcome to E2E!

The main tradeoff of the solution you shared with ADS124S08 is that you cannot have differential filtering. You could put a single-ended filter for each odd AIN channel + AINCOM, but Joseph recommended that schematic if you don't need any input filtering.

This is the input schematic for the ADS1261EVM:

You would have to modify the channels you use for the IDAC output to remove the filtering. You could remove the capacitors and replace the series resistors with 0ohm resistors.

Thanks,

Maggie

ADS1282-SP: [ADS1282-SP] Calibration via OFSCAL/GANCAL commands without continuous mode

Xavier Hache — Tue, 07 Jul 2026 18:02:24 GMT

Part Number: ADS1282-SP

Datasheet of ADS1282-SP shows to stop continuous operation before and to resume continuous operation after transmitting OFSCAL/GANCAL commands. However, we want to operate the device in read-by-command mode and would prefer to not have to transmit superfluous commands (i.e. RDATAC and SDATAC) following a calibration command.

Is it possible to calibrate while the device is in read-by-command mode?
What are the disadvantages (if any) of doing so?

RE: ADS1282-SP: [ADS1282-SP] Calibration via OFSCAL/GANCAL commands without continuous mode

Keith Nicholas — Wed, 08 Jul 2026 19:58:50 GMT

Hello Xavier,

If you do not send the RDATAC command after SYNC and after OFSCAL or GANCAL, then the DRDY signal no longer toggles and simply stays at a high level. I recommend using the above sequence in Figure 61 if you are using the CAL commands.

Regards,
Keith

DAC8552: Vdd=5V, can SPI work from 3.3V GPIO

Ben L1 — Tue, 07 Jul 2026 09:48:13 GMT

Part Number: DAC8552

I want to confirm if the DAC8552 can be powered at 5V and receive 3.3V CMOS logic for its SPI bus. Forum post DAC8552 and DAC8532, using 5V supply, is it possible to connect to 3.3V CPU - Data converters forum - Data converters - TI E2E support forums says the answer is yes, but the response references specs of an input low max 0.8V and input high min of 2.4V, which matches the datasheet for the DAC8532, however there is no equilivent spec for the DAC8552. The datasheet for the DAC8551 which is a very similar part spec's an input high voltage of 0.7*Vdd = 3.5V which is very different from 2.4V and would not work to be driven by a 3.3V MCU. Can you confirm which is the accurate spec for this chip and if it can receive 3.3V SPI signals when powered with 5V?

RE: DAC8552: Vdd=5V, can SPI work from 3.3V GPIO

Ben L1 — Wed, 08 Jul 2026 19:28:11 GMT

Not sure how I missed that in the datasheet. Thanks!

RE: ADC124S021: Maximum delay from /CS falling edge to first SCLK and intermittent abnormal output codes

Joel Meraz — Wed, 08 Jul 2026 17:03:31 GMT

Hello Yamashita-san,

My apologies for the delay in response, as I was on leave.

Can you clarify what is the measured input voltage, what is the measured voltage of VA, and what digital output are you receiving?

1. There should not be a limit on the time between the fall of ~CS and when SCLK becomes active. The input signal remains in acquisition for the first 3 SCLK cycles, which does limit the minimum SCLK frequency, as voltage can leak from the sampling capacitor between sampling and conversion phases if too much time elapses and yield an error.

2. We have not observed this behavior. However, it is possible glitches on SCLK can cause desynchronization between the device and controller.

3. If there is an extended amount of time between samples, it is a good idea to bring ~CS high between samples periodically to ensure synchronization.

Are you able to give more information of the timing, such as the time between samples, SCLK frequency, and whether there are any other factors that seem to cause the issue to occur more or less frequently? Can you also share a schematic of the application?

If more time is allowed between samples, or less time between the fall of ~CS and when SCLK is active, is there any difference in how frequently an issue occurs?

Regards,
Joel

ADC124S021: Maximum delay from /CS falling edge to first SCLK and intermittent abnormal output codes

Ryu Yamashita — Fri, 03 Jul 2026 13:06:41 GMT

Part Number: ADC124S021

Hi team,

Since I have not received a reply, I am reposting this.

Background: We are using ADC124S021CIMMX to measure a thermocouple-related signal on IN4. The analog input voltage appears stable, but the ADC output code intermittently changes abnormally. In our current timing, /CS is driven low and the SCLK burst starts approximately 4 ms later. The burst contains 16 SCLK cycles.

Questions:

Is there any maximum allowed delay from /CS falling edge to the first SCLK edge when /CS is held low?
If /CS is held low for several milliseconds before the 16-clock burst, can SCLK glitches or missed edges cause the internal serial state to shift without automatic timeout recovery?
Does TI recommend toggling /CS high after every 16-clock frame to re-synchronize the interface for this device?

Best Regards,
Ryu.

ADC12DJ5200RFEVM: Data Capture board for ADC12DJ5200RFEVM

Adam Bush — Wed, 08 Jul 2026 14:57:34 GMT

Part Number: ADC12DJ5200RFEVM

What is the reccommended data capture board to use with the ADC12DJ5200RFEVM Eval board? The documentation refers to the TSW14J57EVM. However, I can't find this anywhere, and Digikey shows Obsolete?

DDC264: Part Not in Stock

Pietro P — Wed, 08 Jul 2026 14:54:41 GMT

Part Number: DDC264

Good Morning,

I am interested in this part for a first design but the part result not-in-stock on many distributors?

What do you suggest to do?

Thanks,

Regards

AFE5401-Q1: DSYNC1 and DSYNC2, but only one DE pin.

user5883945 — Wed, 08 Jul 2026 14:48:54 GMT

Part Number: AFE5401-Q1

Dear,

The customer wants to use AFE5401 ADC for their new project, with STM32 processor and plans to use its PSSI (Parallel Synchronous Target Interface) parallel interface to receive ADC data,
But the ADC has two synchronization signals: DSYNC1 and DSYNC2. The parallel interface of the processor only has one DE pin that can connect to this signal, which is used to indicate that the data at the receiving end is valid (frame synchronization function can be used),
There are no other pins with similar functions, so there are two questions that need your help to confirm:
1. Is DSYNC2 also the same as DSYNC1: aligning the rising edge with channel 1 data? If so, can we use only the DSYNC2 line to start sampling from CH1 each time and then collect a fixed number of points, as long as the sorting of the sampled data is always from CH1 to CH4, and there will be no channel confusion in the subsequent algorithm data collection?
2. Does DSYNC1 have to be used? Are there multiple rising edges in the collection of multiple points? Why is there no rising edge at the position CH1 data point - DSYNC1 that I marked in the following figure? How has the timing of DSYNC1 changed specifically?

RE: AFE4490SPO2EVM: Need Altium designer files for AFE4490SPO2EVM

Payton Schubel — Wed, 08 Jul 2026 14:29:38 GMT

Hello Sunil,

Let me follow up with you via email.

Regards,

Payton

AFE4490SPO2EVM: Need Altium designer files for AFE4490SPO2EVM

Sunil Tank — Fri, 03 Jul 2026 11:06:30 GMT

Part Number: AFE4490SPO2EVM

Hello,

We urgently required hardware design files of AFE4490SPO2EVM for Altium or any other designer tool .

It will be great help if you provide that.

Thanks for your support.

DAC904: Did DAC904 remine active for the next years

dov segal — Wed, 08 Jul 2026 11:32:11 GMT

Part Number: DAC904

Did DAC904 remine active for the next years

RE: ADS1282-SP: [ADS1282-SP] Calibration via OFSCAL/GANCAL commands without continuous mode

Xavier Hache — Wed, 08 Jul 2026 10:44:58 GMT

Hello Keith,

Would the following sequence work if using calibration commands (commands crossed red are not executed)? Would nDRDY still behave like shown in the figure?

RE: DAC63204: DAC63204 design questions

Logan — Wed, 08 Jul 2026 10:35:50 GMT

Thanks,refer to your response,we plan to use 4.02K.

There are some other questions.

1.Idac tolerance range,from above application VDD1 we can calculate Idac maximum is 149uA when R3 value set to 4.02K [(0-0.6)/4.02=149uA] ,we are worry about whether this current is too large for the DAC63204 output PIN.

2.Below is another use case,VDD2 voltage is 1.01~1.12V,typical is 1.05V,Vdac=0~1.8V.considering with E-96 series calculate R3 value is 7.15K.Could you help me check if this value is correct?

DAC63204: DAC63204 design questions

Logan — Tue, 07 Jul 2026 01:54:04 GMT

Part Number: DAC63204

Hi Ti teams

Currently,we plan to use the DAC63204 as DAC to regulate the output voltage of the TLV62569 and the TPS548A23,use the ADS1015L as ADC to measure remote feedback.There are some questions:

1.Is this design feasible?

2.As shown in the picture above,VDD1 voltage is 1.7~1.95V,Vdac is 0~1.8V,R1/R4 value is fixed,according to the calculation formula "Vout =Vfb(1+R1/R2)-R1/R3*(Vdac-Vfb)" ,the Rdac=4.058K,right?

If above right,R3 value need <4.058K. If Rdac value set to 1K same as R4,the Vout calculation formula "Vout =Vfb(1+R1/R2)-R1/R3*(Vdac-Vfb)" is easier,which resistance value or any other value would you recommend.,4.02K or 1K or other?

2.DAC63204 I2C port pull up voltage support 1.8V right? Can the DAC63204 I2C port be directly connected with ADS1015L, then connected to host through level shift.

3.From SPEC seems pin.cap need use 1.5uF capacitor connect to AGND,can this cap value use 1uF?

4.If use Pin.VREF, then directly connect to power rail same as VDD,is this way okay?

If not use Pin.VREF, then place 100nF cap to GND and through 10K res connect to VDD rail,right?

ADS8698: Design support

Rakesh Reddy Yara — Wed, 08 Jul 2026 09:05:57 GMT

Part Number: ADS8698

Dear Support Team,

We are using the ADS8698 device in our circuit and would appreciate your guidance on a few points regarding the analog input stage.

Our analog input voltage range is ±10 V. Could you please clarify whether an external operational amplifier is required at the analog input, or if the ADS8698 can interface directly with this input range?

Additionally, our design requires overvoltage protection (OVP) up to ±20 V. The ADS8698 datasheet also mentions an OVP rating of ±20 V, but it does not clearly specify the reference point for this rating. Could you please clarify whether the ±20 V OVP is specified with respect to AGND (analog ground) or another reference?