Data converters forum - Recent Threads

ADS7830: ADS7830: Is SCL fall time below the Fast-mode minimum specification acceptable?

Kyohei — Fri, 30 Oct 2026 08:55:24 GMT

Part Number: ADS7830

Hi team,

I have a question regarding the ADS7830 I2C SCL fall-time specification.

Our customer is currently evaluating the ADS7830 and uses the I2C interface in Fast mode.

According to the ADS7830 datasheet, the minimum SCL fall time (tFCL) for Fast mode is specified as:

tFCL(min): 20 + 0.1CB ns
tFCL(max): 300 ns

However, the measured SCL fall time on the customer's board is approximately 432 ps, which is significantly faster than the specified minimum value.

The measured waveform is clean, and no significant ringing, overshoot, or undershoot is observed.

We also found the following TI E2E discussion for the TCA9539:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/723840/tca9539-i2c-input-rise-and-fall-time-for-fast-mode

In this thread, TI mentioned that a faster input rise/fall time below the datasheet minimum is acceptable for the device.

Could you please clarify the following for ADS7830?

Is an SCL fall time of approximately 432 ps acceptable for the ADS7830 in Fast mode, even though it is below the datasheet tFCL minimum specification?
Does the tFCL minimum specification represent a functional limitation of the ADS7830 input circuitry, or is it primarily specified for compliance with the I2C bus timing/EMI requirements?
If the waveform has no significant ringing, overshoot, or undershoot, is there any concern regarding device functionality or reliability with such a fast SCL falling edge?

Best regards,
Kyohei

ADS131M04: ADS131M04 emits status word from NEXT transfer in place of CRC word 25% of the time

Tariq Singh — Fri, 30 Oct 2026 06:20:57 GMT

Part Number: ADS131M04

Hi,

I have an issue where the ADS131M04 emits the status word from the next transfer (0x500000) in place of the CRC (0xYYYY00, where Y are the CRC bytes). I believe this to be exactly the same problem as this post.

I have some waveforms below. This first capture shows a bad frame, the part indicated in red is where the CRC is meant to be present but is not. The bytes 0x500000 seem to indicate that the next status word was emitted, as that would indeed be 0x500000.

Below is a normal, error-free frame:

These errored frames do not occur with any pattern or correlation that I can recognise. I have tried changing CLKIN speed, SPI speed, delays around the start/end of the transfer, drive strengths from the MCU, and under all conditions this 24% - 25% error rate is maintained almost exactly. Note also that this was working error-free just a few days ago, but I have not been able to get back to that state (chip damage?).

My current hardware setup:
- STM32G071RB Nucleo using SPI1 and various GPIO, SPI using interrupt-based non-DMA transfers
- SPI CPOL=0, CPHA=1, Speed = 4 MHz, 8 also tried
- CLKIN = 4 MHz, 8 also tried
- Sampling rate for logic analyser captures is 24 MHz

I would greatly appreciate some help here. It seems like that other post had almost exactly the same issue.

DAC43701: Schematic Review

Allan Fan — Thu, 29 Oct 2026 08:59:58 GMT

Part Number: DAC43701

Hi experts,

Would you please support to review the schematic of DAC43701? It's used to output adjustable Vref for comparator TLV3601 for core power(0.65/0.75/0.85V) monitoring.

Thanks,

Allan

RE: DAC43701: Schematic Review

James Steenbock — Thu, 29 Oct 2026 23:20:28 GMT

Hi Allan,

The schematic shows the DAC43701 OUT pin (pin 8) directly tied to the TLV3601 OUT pin (pin 1). To use the DAC43701 as a VREF source, it should be connected to one of the TLV3601 comparator inputs to serve as the reference threshold.

Let me know if I am misunderstanding the setup. Right now, it seems like there would be some contention between the DAC output and comparator output.

Regards,

James

DAC121S101: Multiple DAC121S101 Control

Ryan Pang — Thu, 29 Oct 2026 21:22:42 GMT

Part Number: DAC121S101

I've got a benchtop setup that uses multiple DAC121S101s. I have the EVM set up and can control a single EVM board with a LaunchPad. I'd like to know whether it's possible to control multiple DAC121S101s through the EVM software using an MSP430F5529 LaunchPad.

I realize I could write my own firmware to control multiple DACs with the MSP430, but it would be convenient if this were possible using the existing software tools.

RE: ADS131M04: Component top marking with different policy

Mason Marrero — Thu, 29 Oct 2026 21:10:11 GMT

Hi Vincent,

Welcome to the E2E forum and thank you for your interest in our Precision ADCs.

The font can change depending on when it was made and what protocols we had in place at that time. A few years ago the standard for the etching font changed, and it appears that these two products were created around that time. This is likely why you see this change in font.

Regards,
Mason

ADS131M04: Component top marking with different policy

SCHMITT Vincent — Thu, 29 Oct 2026 14:13:52 GMT

Part Number: ADS131M04

I have two batches of components with part number ADS131M04IRUKR. The package marking complies with the TI marking standard, but the font is different. Is this normal?

BOOSTXL-ADS8688W: ADC Conversion Result Apparent Offset Error

William Santos — Thu, 29 Oct 2026 19:44:24 GMT

Part Number: BOOSTXL-ADS8688W

Hello,

I am using a TM4C1294 Launchpad with the ADS8688 Boosterpack plugged into the second boosterpack header pins on the launchpad. I am able to communicate with the ADS8688 and receive conversion results, however the results are about 0.5V off from 3.3V (~2.75V). I have the channel input configured to be single ended. What is causing this offset? It does not appear to be my firmware

RE: BOOSTXL-ADS8688W: ADC Conversion Result Apparent Offset Error

William Santos — Thu, 29 Oct 2026 20:38:55 GMT

hi Yolanda,

Thank you for your quick response. The boosterpack is populated with what came from Digikey which is ADS8688W.

RE: BOOSTXL-ADS8688W: ADC Conversion Result Apparent Offset Error

Yolanda Gonzalez — Thu, 29 Oct 2026 20:19:48 GMT

Hello Will!

Glad to hear you are using the ADS8688W boosterpack!

Just to confirm, the boosterpack should come with an ADS8688W device populated, not an ADS8688. The parts are, in most aspects, the same.

The differences are:

The input range:
- the ADS8688 has a max ±2.5xVREF range
- the ADS8688W has a max ±3xVREF range
Input architecture capability
- the ADS8688 SE only
- ADS8688W SE & differential

I am thinking the offset is due to a scaling error. Or did you re-populate the boosterpack with an ADS8688?

Best regards,

Yolanda Gonzalez

RE: ADCS7476: Max reflow temp question

RahulVK — Thu, 29 Oct 2026 18:16:43 GMT

Hi Robert,

The discrepancy you are seeing is due to the difference between legacy soldering specifications and modern, lead-free reflow standards.

For the ADCS7476AIMF/NOPB, the correct peak reflow temperature is 260°C, as indicated in the Packaging Information table 1. The 215°C figure listed under "Absolute Maximum Ratings" is a legacy specification for infrared soldering 2.

In modern assembly, the 260°C rating refers to the peak temperature classification for lead-free, RoHS-compliant components according to the JEDEC J-STD-020 standard 1. When using this higher temperature, you should follow a standard lead-free reflow profile rather than the older 10-second infrared limit.

For the specific time-at-temperature duration and the full profile requirements, please refer to the JEDEC J-STD-020 standard, which governs the "Level-1-260C-UNLIM" classification listed in the packaging table 1. Additionally, it is recommended to check the specific reflow parameters provided on your device's shipping label or your assembly house’s guidelines, as these are tailored to the specific lead-free process being used 3.

ADCS7476: Max reflow temp question

Robert Olson1 — Thu, 29 Oct 2026 16:52:25 GMT

Part Number: ADCS7476

The datasheet for ADCS7476AIMF/NOPB has an "Absolute Maximum Ratings" table on the tob of page 4 showing that the Maximum "Soldering temperature, infrared (10 sec) " is 215°C, but the "packaging information" table on page 28 shows a max reflow temp of 260°C. Can you please confirm the correct max reflow temp and time?

ADS8681: ADC recommendation for low-frequency photodetector signal acquisition with small amplitude fluctuations

Carlos Pérez — Thu, 29 Oct 2026 15:02:17 GMT

Part Number: ADS8681

Hello Texas Instruments Support Team,

I am looking for a precision ADC suitable for acquiring a signal from a photodetector, and I would appreciate your help in selecting an appropriate device and evaluation board.

I have already reviewed your ADC product portfolio and compared several available options. However, given the wide range of devices and specifications, I have not been able to identify a clear preferred candidate for my particular application.

Signal characteristics:

The photodetector output has a relatively large DC component (typically around 0.5 V, although this value may change depending on the experimental conditions), with small amplitude fluctuations superimposed on it, typically on the order of tens of millivolts.

The frequency content of interest is mainly between DC and 1 kHz, including relevant components at frequencies as low as tens of Hz. However, I would also like to retain the possibility of acquiring signals with bandwidths extending to several tens of kHz in future applications.

My main concern is achieving sufficient effective amplitude resolution to accurately capture these small fluctuations despite the relatively large DC component.

ADC requirements and preferences:

High resolution and low input-referred noise, prioritizing effective resolution (ENOB) over nominal bit depth.
Bipolar analog input range of at least ±1 V, preferably with configurable input ranges. I would like to avoid an unnecessarily wide input range, as this would reduce the voltage resolution available for the small amplitude fluctuations.
A sampling rate of at least 1 MSPS would be desirable, providing flexibility for future applications and digital filtering.
Preferably a single-ended analog input, to avoid additional differential signal conditioning circuitry.
SPI digital interface preferred, although I would be open to alternative interfaces if they provide significant advantages.
Availability of an official evaluation board to characterize the ADC before integrating it into the final system.

RE: ADS8681: ADC recommendation for low-frequency photodetector signal acquisition with small amplitude fluctuations

RahulVK — Thu, 29 Oct 2026 18:06:03 GMT

Hi Carlos,

There are few ways to accomplish this.

AC coupling the photodetector circuit with the ADC driver will help remove the varying DC offset and retain the AC content. However, the high-pass filter will impact frequencies closer to DC.
Use a high dynamic range, high resolution ADC like the ADS8900B. Most >100dB dynamic range ADCs will be differential input and a FDA like THS4551 can help convert single-ended signal to differential.
If the target dynamic range is in the ~90dB range, then a single-ended input ADC like the ADS8860 would be appealing.

Regards,
Rahul

ADS8688W: Request for Corrected Datasheet and Technical Confirmation – ADS8688WDBTR

Sandhya G — Fri, 16 Oct 2026 10:46:07 GMT

Part Number: ADS8688W

Dear Texas Instruments Support Team,

During our technical validation of MPN ADS8688WDBTR, we identified the following documentation discrepancies:

The device comparison table in the datasheet lists ADS8674 and ADS8678, which do not correspond to the requested MPN ADS8688WDBTR.
The packaging information section displays the package and pin details for ADS8688WDBTR as “null (null)”, instead of specifying the applicable package type and pin count.

Kindly confirm the following:

The correct package type and pin count for ADS8688WDBTR

We also request you to provide the latest corrected datasheet for ADS8688WDBTR, including the correct device comparison, package, and pin information.

The relevant screenshots are attached for your reference.

Your clarification and the corrected datasheet will help us complete our internal technical validation.

RE: ADS8688W: Request for Corrected Datasheet and Technical Confirmation – ADS8688WDBTR

RahulVK — Thu, 29 Oct 2026 14:07:46 GMT

Hi Sandhya,

ADS8688WDBTR uses the DBT package — 38-pin TSSOP, 9.70 mm × 6.40 mm — per TI's part details 1 and quality/packaging report 2.

We appreciate your feedback about the datasheet, and it is under revision now. The revised document is expected to be online in around 4 weeks.

Regards,
Rahul

DAC80501: Schematic review of DAC80501ZDGSR

AP — Thu, 29 Oct 2026 13:39:37 GMT

Part Number: DAC80501

Laser diode driver.pdf

Hello TI Team,

We have designed a laser diode driver circuit using the DAC80501ZDGSR, OPA197IDR, and LMR33630ARNXR. We would appreciate it if your team could review the circuit and provide feedback on the design, along with any recommended modifications.

Our laser diode module supports two wavelengths, 980 nm and 1470 nm, with a maximum current requirement of 18 A. To meet this requirement, we are planning to use the LM5176PWPR DC-DC converter to supply power to the laser diode.

For the driver circuit design, we referred to your application document: https://www.ti.com/document-viewer/lit/html/SBAA782

I have attached the laser diode module datasheet, Beijing RealLight-R7M-638+980+1470nm Module Data, for your reference. Beijing RealLigh-R7M-638+980+1470nm module data (2).pdf

Could you please review the schematic and provide your feedback on the following points?

The overall circuit design and component selection.
The suitability of the proposed DC-DC converter for the required laser diode current.
Any potential design issues or improvements needed to ensure reliable operation.
Any recommended modifications to the schematic.

Your feedback would be greatly appreciated and would help us validate the design before proceeding with hardware implementation.

Thank you for your time and support.

DAC0802: TI alternative solution to LTC2601IDD#PBF

Sean Liao (Yu-Sheng) — Thu, 29 Oct 2026 13:12:13 GMT

Part Number: DAC0802

Hi sir,

pls provide TI alternative solution for LTC2601IDD#PBF.

P2P is nicer!

Thanks a lo

ADS124S08EVM: PGA Gin

John Boecker — Fri, 16 Oct 2026 16:15:49 GMT

Part Number: ADS124S08EVM

I am running the predefined Current Measurement script on the ADS124S08EVM board. 5 mV is appplied across the current shunt resistor R78. The mean reading on the Time Domain tab in the Analysis Engine is 15197 with PGA gain of 1. With no input to J9 pins 2 and 3 (across R78) the mean offset is 127. If the gain is changed to 2, the mean reading is 20612. I expected something closer to two times 15197 or 30394. Likewise with PGA gain of 4 I get 24170 and I expect 60788. What am i not understanding?

RE: ADS124S08EVM: PGA Gin

John Boecker — Thu, 29 Oct 2026 13:00:03 GMT

Hi Dale,

I biased VINN up off ground and can now see the mean change by two as the PGA gain changes by two. I tried to meet the requirements of Figure 51 in the ADS124S06 datasheet.

This can be closed. I cannot get Ti’s web site to work correctly.

TX7332EVM: TX7332EVM: Output burst stops increasing when Repeat Count exceeds 4

LJ Z — Thu, 29 Oct 2026 09:24:36 GMT

Part Number: TX7332EVM

Dear TI Support Team,

I am using the TX7332EVM in on-chip beamforming mode for an ultrasound research project. My target output parameters are:

Carrier frequency: 1 MHz
Burst duration: 200 µs, equivalent to 200 cycles per burst
Pulse repetition frequency: 1 kHz
Burst duty cycle: 20%
Total operating time: 20 minutes
Output voltage: ±15 V

However, increasing Repeat Count does not extend the output beyond approximately 40 µs.

My pattern configuration consists of 16 alternating PHV/MHV segments, forming 8 complete cycles, with PERIODS = 23 for all segments and CLK_DI = 2.

Measurements taken directly at the TX output using an oscilloscope show:

Repeat Count = 0: 8 cycles.
Repeat Count = 1: 16 cycles.
Repeat Count = 5: approximately 40 cycles, rather than the expected 48 cycles.
Keeping Repeat Count = 5 and changing CLK_DI from 2 to 3: approximately 20 cycles at 0.5 MHz.

The last two cases both correspond to a burst duration of approximately 40 µs.

Could you please clarify the following?

What is the valid range and counting convention for Repeat Count? Is there any limitation to a value of 4?
Could the EVM’s default CPLD timing, GUI configuration, or dynamic power control truncate the output at approximately 40 µs?
Can the target parameters listed above be achieved using the standard EVM hardware, GUI, and firmware?
If so, could you provide the required register settings or an example configuration? Would any CPLD firmware modifications be necessary?
Are there any thermal, power, or load restrictions for operating at ±15 V and a 20% burst duty cycle for 20 minutes?

I can provide screenshots of the GUI settings and oscilloscope waveforms.

Thank you for your assistance.

Best regards

ADS4245: ADC Burnout Specification

Benjamin Chng — Thu, 01 Oct 2026 02:59:20 GMT

Part Number: ADS4245

Hi, I would like to understand what the burnout specification of the ADS4245 is. It is not specified in the datasheet. Thanks.

RE: ADS4245: ADC Burnout Specification

Benjamin Chng — Thu, 29 Oct 2026 05:28:34 GMT

What is the input power level (analog input signal) that would damage the ADC?

RE: ADS8688W: Request for Corrected Datasheet and Technical Confirmation – ADS8688WDBTR

Sandhya G — Thu, 29 Oct 2026 03:47:55 GMT

Hi Yolanda,
Good day!

This is a gentle reminder regarding the corrected datasheet for ADS8688WDBTR, including the applicable device comparison table, pin configuration, and packaging details.

Could you please provide an estimated date by which the corrected datasheet will be available? This information will help us plan and proceed with our technical validation and compliance activities.

Looking forward to your earliest response.

Thank you.

Best regards,
G. Sandhya

TXS0102: Body nmarkings

N Swad — Thu, 08 Oct 2026 09:31:01 GMT

Part Number: TXS0102

Dear TI Support Team,

**Part:** TXS0102DCUR – Level Translator
**Datasheet:** SCES640L – January 2007, Revised January 2026

The datasheet addendum lists the possible device body markings as **35ST, FE, NFEQ, NFER, and NZ**.

We purchased the devices in two lots, in March and July 2026. The devices marked **35ST** are working as expected, whereas the lot of 210 devices marked **FE and NZ** is not working as expected.

Could you please clarify the difference, if any, between these body markings? Are there any differences in the silicon revision, electrical characteristics, or functional behaviour associated with these markings?

Please also advise whom we should contact for further technical clarification.

Regards,
Nikhil Swadia
Agile Design Services

+91 6201750385