https://e2e.ti.com/support/data-converters-group/data-converters/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1685472/dac7728-clarification-regarding-a-question-about-the-datasheet/6520695Mon, 26 Oct 2026 07:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9c13902e-a713-4387-a6bd-9b2d673703e7Kobayashi OsamuHi Erin, thank you for your prompt reply. With the OFFSET DAC code set to &quot;2ABh&quot;: The DAC output voltage is -10V when the DAC output data is &quot;800h&quot;. The DAC output voltage is +10V when the DAC output data is &quot;7FFh&quot;. The DAC output voltage is 0V when the DAC output data is &quot;000h&quot;. To reiterate, the circuit conditions are as follows: AVDD to AGND = +15V; AVSS to AGND and DGND = -15V; DVDD to DGND = 5V; IOVDD to DGND = 3.3V; REF-A and REF-B to AGND = 5V; GAIN = 4. Thank you for your continued support. Best regards, Osamuhttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1689194/ads7253-need-guidance-to-select-right-adc/6520681Mon, 26 Oct 2026 07:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:59ea3e03-97c3-4522-93e2-3bf9bc9aba03Naveen K1Hi, Good Day! Could you please advice for the above Queries. Thanks and regards, Naveen Khttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1687974/txs0102-body-nmarkings/6520584Mon, 26 Oct 2026 05:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:db24eb5f-fdb0-43b6-b1bd-3c9a2e231d4cN SwadWe are Contract manufacturer and wont know how to generate waveforms of both the 35ST device and the FE/NZ marked device. The cards we made were rejected. This has to do something with 1.8V sensitivity on VCCA. This device was used for converting 3.3V to 1.8Vhttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1691696/afe882h1-afe882h1-is-receive-gap_err-detection-gated-by-carrier-detect/6520511Mon, 26 Oct 2026 03:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8424b78b-9920-4d7c-8667-23bcefde1d94Mehul DalalHi Joseph, Thanks a lot on the detailed answers. I believe the answers provided are good enough to understand the GE scenario in different cases. I am marking this thread as resolved. Mehulhttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1692435/dac8742h-where-can-i-find-the-ff-pa-reference-design-mentioned-in-sbaa367Sun, 25 Oct 2026 10:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d435c41d-1698-4e79-acc7-d7cf900bb8b3Parul NawariaPart Number: DAC8742H Other Parts Discussed in Thread: PROFIBUS , , DAC8740H , TIDA-060020 , TIDA-01504 Hi, I am designing a loop-powered PROFIBUS PA field transmitter using the DAC8742H. The application brief SBAA367, “Designing Foundation Fieldbus and Profibus PA Devices with the DAC874xH Modem Family” (March 2019), refers to an “FF/PA reference design” in two places on page 2: Figure 3 (Bus Voltage with FF/PA Signal Transmitted) was measured with the FF/PA reference design using the DAC8742H, with &#177;9 mA modulation at 16 mA DC. The “Physical Layer Compliance” section points to the FF/PA reference design for more information on physical-layer testing. I could not find this reference design on ti.com. The DAC8740H/41H/42H product pages list only TIDA-01504 and TIDA-060020, which are both HART designs. please share the TIDA number or a link to the schematic, BOM and design guide for FF/PA reference design.ProfibusIndustrial AutomationTIDA-01504DAC8740HTIDA-060020DAC8742Hhttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1692422/adc128s052-q1-data-converterSat, 24 Oct 2026 16:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bfa01f8d-35f3-4828-b623-ae52a7ae688bNishant GuptaPart Number: ADC128S052-Q1 Hello TI Team, I am measuring approximately 32–35 digital counts from the ADC when the input voltage is 0 V. I would like to clarify the appropriate method for correcting this offset. If the measured ADC count at 1 V is x , can I simply subtract the zero-input offset (approximately 32 counts) from the measured value to obtain the corrected reading, or should I provide an external offset adjustment through the amplifier circuit? Would an external offset adjustment offer any advantage over software-based correction? Additionally, if the zero-input ADC count changes with temperature or operating conditions, how can this offset be calibrated onboard? Should I implement an adjustable offset provision in the amplifier circuit, or would software-based calibration be sufficient? Please recommend the best approach for achieving accurate and stable ADC measurements. Thanks &amp; Regards, Nishant GuptaADC128S052-Q1Aerospace &amp; Defensehttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1692420/ads131b04-q1-altium-design-files-for-ads131b04-q1evmSat, 24 Oct 2026 16:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cf26dc80-f725-44db-9b68-386130a72831William FosserPart Number: ADS131B04-Q1 Hi, Are you able to share the refernce design ADS131B04-Q1EVM Altium design files with us? We are a student solar racing team that would like to have a closer look at this design to evaluate the use of ADS131B04-Q1 for our BMS. Best, William Nordlys NTNUADS131B04-Q1HybridADS131B04-Q1EVMelectric &amp; powertrain systemshttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1691625/afe58jd28-similar-device-with-32-or-64-channels/6520301Sat, 24 Oct 2026 12:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f56d3b96-3a2a-42e4-bc87-8f9fa6f93949Sheetal GuptaIn AFE58JD32, ADC performance is same as AFE58JD28 except that the maximum sampling rate is half compared to AFE58JD28. VCA noise in AFE58JD32 is higher compared to AFE58JD28. However, AFE58JD32 offers more number of channels integration. Currently, we don&#39;t have a device which has same performance as AFE58JD28 with higher channel count.https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1687548/afe5401-q1evm-evaluation-of-afe5401/6520298Sat, 24 Oct 2026 11:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2ff17bed-e001-473b-a61b-edd5857d1bd5Sheetal GuptaTSW1400EVM is the FPGA EVM used to capture AFE5401 datahttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1689233/afe5832lp-afe5832lp-spi-confiquration-works-with-jtag-but-fails-after-zyng-sd-card-boot/6520293Sat, 24 Oct 2026 10:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cc2d3e6d-7022-4570-9c34-bd0119411c48Sheetal GuptaHi Kangwei, Is there a way in the hardware to directly probe the SPI signals which are going to AFE5832LP using oscilloscope. Basically, you can probe the SPI signals in both the cases when JTAG is being used vs with SD card and confirm if they look as expected.https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1689526/afe5809-unexpected-long-and-varying-sync-word-delay-time/6520291Sat, 24 Oct 2026 10:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a4762acd-55be-495e-bb8a-c78ba82bc5f2Sheetal GuptaHi Morten, This behavior seems quite unexpected because the delay between TX_TRIG pulse and SYNC_WORD is a fixed delay and it shouldn&#39;t be as high as 1ms. Can you please confirm that while applying external TX_TRIG signal, the pulse width of TX_TRIG signal is as long as 1 ADC clock cycle?https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1692201/ads127l11-current-limit-of-esd-cell-at-input-pin/6520280Sat, 24 Oct 2026 05:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:469e9b28-ca62-4ded-be22-1adf27930ff1MochiHi Keith, Thank you very much for your valuable reply. We have well understood the limitation of ESD cell and concern of might occur latch up by chance. And proceeding ES-proto evaluation. Regards, Mochizukihttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1692399/ads9817-parallel-spi-configurationSat, 24 Oct 2026 04:49:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b2a5c6f6-1a7d-46df-99da-ceb2ac0b7d8fMOHD AKBARPart Number: ADS9817 Hi TI Team, We plan to use two ADS9817 ADCs to monitor eight +5 V and eight −5 V supply outputs wrt the gnd. We have the following questions: Can both ADCs share SCLK and SDI ,SDO with separate CS signals? When one ADC&#39;s CS is inactive (HIGH), does its SDO output enter a high-impedance (Hi-Z) state Can both ADCs share the same SMPL_CLKP and SMPL_CLKM signals to synchronize sampling? I have attached -5V sensing ADC configuration , please check and let us know if there is any issue or precaution must be followed for sensing -5V wrt the gnd. Please confirm whether this configuration is supported and highlight any design considerations. Thank you.ADS9817https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1692395/afe4950evm-afe4950evm-request-for-bio-sensing-gui-and-acquisition-softwareSat, 24 Oct 2026 02:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fc72ed3a-fbed-4d12-8a71-c28836b6cfaeKarthika PotailPart Number: AFE4950EVM Hello TI Support Team, I&#39;m working on a university research prototype using the TI AFE4950EVM to acquire synchronized ECG and PPG signals. I&#39;ve successfully connected the board to my Windows laptop, and it is detected through COM3 and COM4. However, I&#39;m unable to find the AFE4950EVM acquisition software. Could you please clarify: Are Bio-Sensing_Installer_V5.3.exe and AFE4950EVM_Installer_V2.0.exe publicly available? If not, what is the process for requesting access to these installers? Is there a publicly available SDK or communication protocol for acquiring ECG and PPG data directly through Python? I would appreciate any guidance or download links. Thank you!AFE4950EVMhttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1691183/dac161s997-temperature-dependence-of-dac161s997/6520257Sat, 24 Oct 2026 00:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f3ce7fcb-008d-4225-9180-0f5279678b8aJoseph WuNiek, I&#39;m sorry I was out of the office earlier this week and didn&#39;t have a chance to answer this question. I&#39;m not sure I&#39;ll have all the answers on the specifications. This device was originally designed by National Semiconductor in 2013 and is part of TI&#39;s catalog because of the acquisition. I&#39;ll go through the calculations based on your data to just to check them. Here, the full scale range is 0mA to 24mA, but gain error and offset are calculated from measurements at 4mA and 20mA. Gain and offset are calculated from slope of the line and the y intercept from these measurements. If you imagine the calculated line as y=mx+b, the difference of m from ideal is the gain error and b is the offset. The offset calculation is all based on the calculation for b. I think that&#39;s the way you understand the measurement, but I wanted to verify that. When it comes to the drift, I&#39;m not sure what they did for the specification listed in the datasheet. They may have used an endpoint check, determining the values at -40C and 105C and then calculated the drift over the 145C for the span of the temperature. Another way they could have done it would be to take the drift from 25C to -40C and then take the drift from 25C to 105C. After that, you could take the max of the two measurements as the specification. Regardless, one of those two would be the typical way to have calculated the drift. Looking at your data, it looks like you&#39;ve already normalized it to the room temperature of 23C. However, we can do some calculations to check the result. Just by inspection, it looks like the linearity of the plot is about 1uA to 1.5uA (removing the noise in the measurement). That&#39;s within the expected -1.5uA to +2.6uA linearity listed in the datasheet. That gives a quick check of the measurements. I have the following estimates for the errors at the 4mA and 20mA measurements, based on your graph: -40C error - 4mA=3uA, 20mA=4uA 23C error - 0uA for both because the result has been normalized 80C error - 4mA=-4.5uA, 20mA=-11uA From these values, I made a calculation for the equivalent offset voltage: -40C offset error - 2.75uA 23C offset error - 0uA again because the result has been normalized 80C offset error - -2.88uA From these values the offset drift is -1.82ppmFS/C from -40C to 23C, and -1.9ppmFS/C. Compare this to the 0.48ppmFS/C listed in the datasheet. The value you&#39;ve shown is higher than what is in the datasheet, so there might be some issue there. I think the typical change in output would be 0.7uA over 60C. Looking at the gain error, you can take the error measurements at 4mA and 20mA and divide by 16 which would give the equivalent error over the full scale. At -40C, the gain error is 62.5ppmFS, while at 80C the gain error is -406ppmFS. Dividing by the equivalent temperature spans, the first becomes -1ppm/C, while the latter becomes -7.1ppmFS/C. Neither of these numbers are far from the typical specification of 5ppmFS/C. In this measurement, the difference isn&#39;t in the gain error, but rather the offset. I&#39;m not sure what might account for this. There might be some issue in the normalization, but the offset shouldn&#39;t be better than what we&#39;ve calculated here. There might be some problems in setting values after turning on the device, or issues with measurements over the temperature span (measuring at 80C instead of 105C), but it wouldn&#39;t affect the -40C values. Another issue might be reference settling over time. In that case, I would think you&#39;d see more non-linearity curving in the measurement. Let me know if you think I&#39;ve made an error in my calculations. Do you have the original, non-normalized data values? Are you measuring a voltage with the DMM across a load resistor? or are you using the DMM as an ammeter? On your board, are there any TVS diodes in parallel with the input that could cause some amount of leakage that isn&#39;t accounted for? Can you share the schematic? Joseph Wuhttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1688797/afe782h1-design-a-4-20ma-circuit-compatible-with-4-wire-and-2-wire-configurations-using-afe782h1-afe882h1/6520143Fri, 23 Oct 2026 20:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:18b47e14-b15c-4d21-9895-40c0476f5593Joseph WuHi, 1) This looks ok to me. The diode was used to latch the RX_IN to the PVDD so that the pin did not go high voltage and become damaged at startup. Using the XTR200, the output is used for an active IOUT mode. 2) I&#39;d like to see how the circuit of #1 is connected to this circuit. There may be interactions between the two circuits because of loading at the XTR200. Show where the relays are connected change between active and passive current modes. It would be helpful to see more of what is intended. Also in this circuit, I think you&#39;re missing the two resistors that set the current in the loop. The current coming from VOUT and VREFIO should set a current going to the IOUT-. Note that IOUT- is not connected to GND, and will be at a voltage below ground. Review the schematic in the datasheet to see what was done on that board. There is an explanation of the current control that should be helpful. Joseph Wuhttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1691696/afe882h1-afe882h1-is-receive-gap_err-detection-gated-by-carrier-detect/6520108Fri, 23 Oct 2026 19:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cf01a575-f202-422f-8995-017748d92c66Joseph WuMehul, I did hear from one of the designers and I did get answers. Responses are numbered same as the questions. 1. Yes. The device does monitor the inter-character gap only while CD is asserted. 2. If the HART carrier disappears or stops, the gap timer stops and does not continue to run for another 11 bit times. 3. The designer wasn&#39;t sure he understood this question. Do you mean can CD_DEASSERT and GAP_ERR both latch the IRQ at the same time? He thought this might be possible. 4. The designer says that gap timer starts more towards the middle of the STOP bit. This is when the bit is detected and confirmed. I believe this is when the bit is latched into the internal clock of the device, so it is not directly at the start of the STOP bit. 5. The gap timer stops at the detection of the next START bit or when CD is deasserted. After that, the MODEM_STATUS bit indicating a gap error is set and is cleared after a read. The read of MODEM_STATUS doesn&#39;t affect the gap timer. 6. The gap timer starts after the first character in a frame, which includes the preamble characters. The carrier should be able to run for an extended period, before the first character, and a GAP will not be asserted. For the two specific cases you&#39;d asked about: Case A: Valid character → continuous 1200-Hz mark for &gt;11 bit times Expected: CD remains asserted; does GAP_ERR assert?[] Yes. The assertion would be between 10.5 and 11.5 bit times. Case B: Valid character → HART FSK carrier disappears Expected: CD deasserts; can GAP_ERR also assert after 11 bit times?[] No. The gap error does not assert. You had also asked about the relationship between different elements in the gap detection state machine with references to different signals. He didn&#39;t have any of this put together and it would take some time to compile it. On top of that, he&#39;ll be out of the office for a couple of weeks. At that point, if need more detailed answers we can revisit this when he returns. For now, I&#39;ll close this thread as resolved. You should be able to ask another question on this thread on Nov. 4 to follow up. If not, you&#39;ll be able to open a new thread. Joseph Wuhttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1692363/ads1299-ads1299-request-for-spice-model-for-kicad-ngspice-simulationFri, 23 Oct 2026 19:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7a0e8723-e1a8-4343-a166-9886af0079b3Himanshi AgrawalPart Number: ADS1299 Hello, I am an undergraduate student at IIT Bombay, working on an EEG circuit using the ADS1299. I am trying to simulate my circuit in KiCad using ngspice, but I could not find a SPICE model for the ADS1299. Could you please let me know if a SPICE model is available for this device, or if there is any recommended approach for simulating it in KiCad/ngspice? I would appreciate your help. Thank you!ADS1299https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1692320/lm5146-need-full-datasheet-with-physical-dimension-and-recommended-latternpattern/6520073Fri, 23 Oct 2026 18:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d9c55c56-d695-4cf5-9cf2-997199ecdeb2Timothy HegartyHi Harish, There is some issue with package dwgs falling off some datasheets. While we resolve this, please use the Q-grade version datasheet https://www.ti.com/lit/ds/symlink/lm5146-q1.pdf for package info. Regards, Timhttps://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1692201/ads127l11-current-limit-of-esd-cell-at-input-pin/6520000Fri, 23 Oct 2026 17:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:97e8bcbd-0274-4904-85be-ab6b685898e7Keith NicholasHello Mochizuki, The ADS127L11 internal ESD cells and internal metal tracks can safely support up to +/-10mA of current. With a single +5V AVDD supply, using a 1kOhm series resistor will limit current to about -8mA worst case when the input swings to -8.5V. (For +8.5V, the maximum current will be about 3mA.) I-in=[-8.5-(-0.5)]/1k=-8mA, or 8mA of current flowing out of the input pin. The -0.5V is the approximate voltage drop of the internal ESD cell with 8mA flowing. Although this condition will not damage the device, the ADC may require a reset to recover proper operation, so this condition should be avoided during normal use. I have tested this condition in the lab on a handful of devices and have never required a reset, but this is not something that we can ensure over all devices. Regards, Keith Nicholas Precision ADC Applications