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ADS4145: ADS4145 sampling speed and other functions

Prodigy 215 points

Replies: 1

Views: 374

Part Number: ADS4145

I am interested in working with the ADS4145 ADC. I had a few questions on this part.

1. The data sheet lists 20MHz as the lowest clock frequency that this ADC can work with. Our application needs 16.5MHz ADC clock speeds. Is this OK ? How low can we go in sampling speed before the ADC  performance goes bad ?

2. We plan to use multiple ADCs in our system and all sampling clocks reaching the ADC will be synchronized. Will all these ADCs be synchronized with this architecture ? Are there any reasons for phase ambiguity in the data due to the ADC architecture ?

3. To enable DC offset correction, is the register write sequence to set EN OFFSET CORR to 1 and then program the offset time constant in register CF ? or is it the reverse order ?

4. I plan to use the ADS4145EVM circuits for my application. Any reasons why the DC offset at the input could exceed +-10mV ? I am just worried if the input DC offset goes over the correction capability of the ADC.

Thanks,

AB

1 Reply

  • Guru 54040 points

    Arvind,

    1. The data sheet lists 20MHz as the lowest clock frequency that this ADC can work with. Our application needs 16.5MHz ADC clock speeds. Is this OK ? How low can we go in sampling speed before the ADC  performance goes bad ?

    A1: We are revising the datasheet to showcase low speed performance. We have seen that part works down to 1MSPS. However the revised datasheet will support speed down to 3MSPS.

    1. We plan to use multiple ADCs in our system and all sampling clocks reaching the ADC will be synchronized. Will all these ADCs be synchronized with this architecture ? Are there any reasons for phase ambiguity in the data due to the ADC architecture ?

    A2: Yes if sampling clock of all ADC chips is synchronized, the output should remain in sync. However, you may consider looking at the ‘Aperture delay’ spec given in timing characteristics table.

    1. To enable DC offset correction, is the register write sequence to set EN OFFSET CORR to 1 and then program the offset time constant in register CF ? or is it the reverse order ?

    A3: Any sequence is correct. SPI writes are sequence independent.

    1. I plan to use the ADS4145EVM circuits for my application. Any reasons why the DC offset at the input could exceed +-10mV ? I am just worried if the input DC offset goes over the correction capability of the ADC.

    A4: DC offset can vary with different lots of ICs. The lot-to-lot variation is most significant contributor of DC offset variation. Supply and temperature variation are other two factors but their contribution in not so significant. The datasheet says the min/max values of DC offset variation are +/-15mV. In an unlikely event, the corner unit may show +/-15mV offset while passing the production test.

    Regards,

    Jim

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