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ADC12J4000EVM: Sample Mapping and Ordering

Prodigy 90 points

Replies: 14

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Part Number: ADC12J4000EVM

I have a question about the sample mapping for the ADC12J4000EVM

I have organized the samples from the JESD204B interface according to Table 12 and Table 13 in the datasheet. However, I am experiencing incorrect results when validating. I just wanted to confirm that I am not misinterpreting the datasheet.

The start of frame for the interface in this design is reading out at '1000', which from the datasheet implies that the bit mapping follows the organization in the attached tables below. Would you be able to confirm that this is correct?

I am using the TSW14J10 breakout board to interface with a Xilinx VC707. 

Thanks in advance, 

Steve M

Sample Mapping [SOF = '1000']

Character Mapping:

  • Hi Steve

    I'm reviewing the information you've provided, I'll respond by Monday am at the latest.

    If you have a data record from the FPGA tools for several frames of data on each lane that might be helpful as well.

    There is one additional feature of the ADC12J4000 that can also help with this. On the ADC12J4000EVM GUI A Control tab, click on the Enable Test Pattern Mode button. This will cause a repeating fixed pattern to be output. The sample values of the pattern are shown in Table 33 of the ADC12J4000 datasheet. Note that this table shows Sample values only, the Tail bits are not included.

    Please also note that on the ADC12J4000EVM the JESD204B data lanes are inverted in polarity. This was done to  optimize signal quality focused routing on these high speed serial pairs.

    The polarity inversions need to be compensated for in the receivers for the ILA and data values to be correct.

    Best regards,

    Jim B

  • In reply to Jim Brinkhurst84999:

    Hi Jim,

    Thanks for the quick response.

    I have attached two raw ILA outputs from the JESD204B block, one configured for signed and the other unsigned through the ADC GUI. It is of a 200MHz signal sampled at 3.76GHz.

    Unfortunately I have been using the ADC12J4000 v1.3 GUI and not the  ADC12J4000 A GUI since I believe we are using an older revision of the board. I tried updating the EEPROM for the 'A' GUI to be able to enable the test pattern. However, I may need to reprogram the EEPROM for compatibility with the 1.3 GUI since I haven't been able to sync with the FPGA build or the high speed data converter pro software with the 'A' GUI. If you have the FTDI configuration template available for the 1.3 GUI it would be greatly appreciated since it is proving difficult to find.

    I have also already compensated for the inverted polarity in the JESD block, thanks for the heads up.

    Steve M

    rx_200_MHz_signed.txtrx_200_MHz_unsigned.txt

  • In reply to Stephen Miller88:

    Hi Steve

    The rev A GUI will not work properly with that revision of board that you have. The clock synthesizer is different between the two boards, so the configuration files of each GUI are only compatible with the board revision it is associated with.

    For the Rev 1.3 GUI you can enable and disable the ADC Test Pattern Mode using the attached configuration files.

    ADC12J4000 EN TPM.cfg

    ADC12J4000 DIS TPM.cfg

    First copy the files here:

    C:\Program Files (x86)\Texas Instruments\ADC12J4000EVM GUI\Configuration Files

    The file settings can be loaded using the Low Level View tab of the GUI. On the Low Level View tab click the Load Config button and select the desired file, then click OK. This will write the necessary register value.

    I'm still working on the 200 MHz data.

    It would be helpful to have the unsigned format data for both Test Pattern Mode enabled as well as signal off (values should be around mid-scale).

    Best regards,

    Jim B

  • In reply to Jim Brinkhurst84999:

    Hi Jim,

    Thanks for the configuration files, I'll get you the test pattern and signal free data hopefully by tomorrow afternoon.

    As for the 1.3 GUI, I overwrote the FTDI template to see if I can upgrade to the 'A' version. Similar to the solution in this forum.

    Unfortunately like I was saying, I can't find the XML template to revert back to the 1.3 GUI capability, so I'm stuck with the inability to even start up the 1.3 GUI outside of simulation mode until I find that template.

    Thanks,

    Steve M

  • In reply to Stephen Miller88:

    Hi Steve

    Sorry, I missed that detail earlier.

    Here is the programming template that should work for that board.

    Everything should be the same as the settings used for the Rev A board except for the Product_Description field.

    ADC12J4000.xml

    Best regards,

    Jim B 

  • In reply to Jim Brinkhurst84999:

    Hi Jim,

    Thanks for the template, it fixed that issue.

    I attached the test pattern and no input ILA data. Both are unsigned.

    Thanks,

    Steve M

    no_input.txt

    test_pattern.txt

  • In reply to Jim Brinkhurst84999:

    Hi Jim,

    Would it be possible to supply an inclusive SDK build for the Vivado reference design to eliminate any uncertainty regarding the HW configuration. I believe I have the correct configuration when cross referencing the datasheet with the values configured within the HSDC GUI. 

    I am setting:

    Sample rate: 3.76G

    Bypass (No DDC)

    Essentially the configuration parameters shown within Table 12 of the datasheet.

    Thanks,

    Steve M

  • In reply to Stephen Miller88:

    Hi Stephen
    I don't have that for the ADC12J4000 at this time.
    There is a very similar Xilinx firmware reference build for the ADC12DJ3200. That device in JMODE0 has a very similar data format to the ADC12J4000 in DDC Bypass mode. The only difference is the lane mapping of the data samples.
    The reference build is in the software section of this page: www.ti.com/.../ADC12DJ3200EVM
    Table 20 of the ADC12DJ3200 datasheet describes the lane mapping for JMODE0.
    Best regards,
    Jim B
  • In reply to Jim Brinkhurst84999:

    Hi Jim,

    I did come across the design for the ADC12DJ3200 on another forum post, and it is how I developed my design.

    I based my mapping table in the initial post off of that design, and confirmed that my implementation matches its layout.

    This is why I initially posted this question, as I do not see the correct output after organizing the samples. I wanted to confirm that my issue was not in this area, and possibly earlier in the chain.

    I find it somewhat odd that the throwaway bits are aligned according to the table. The only samples that appear incorrect are S8-S15, and S24-S31. Then again, these samples may only have an error in the lower 4 bits. However, if this was the case it should manifest in the no signal input.

    If you have any insight it would be greatly appreciated.

    Thanks,
    Steve M
  • In reply to Stephen Miller88:

    Hi Steve

    I haven't managed to work out the cause of the data mapping problems. I think it would be useful to see what is coming on each lane via the debug output display from the de-serializer output. It would be good to cover 2 full frames since that is the duration of the ADC test pattern.

    It would also be useful to enable the JESD204B test pattern modes and use Short Transport Test Pattern. I had a similar question come in recently and looking at that test pattern data for each lane was very useful.

    That exchange is here:

    I hope this is helpful.

    Best regards,

    Jim B

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