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Part Number: ADS4125
i what to sample a fast single pulse analog signal .
sample rate 100MSPS with ADS4125 Parallel CMOS Interface
an FPGA is interface with the A2D
i want to connect a lvcmos 100Mhz clk to the FPGA and A2D
the A2D and the FPGA need to be clk synchronize
1. can i use one low jitter clk 100Mhz 1.8V connected to zero delay buffer 1:2 (1 in , 2 out)
the zero delay buffer will drive 1.8v 100mhz clk to the FPGA and the A2D
2.to sample a fast single pulse is it a problem to use a single ended clk in insted of differantial clk
3. VCM is connected to CLKM is single ended clk input
will VCM be noisy because of that?
1. We suggest you route the clock only to the ADC and use the CLKOUT from the ADC to clock the data into the FPGA using the rising edge.
2. The part performance will be better with a differential input clock, but since you are only sampling a pulse, the single-ended clock input may be good enough.
3. This should not be an issue. I would suggest using two caps for this. Place one cap near the VCM pin and the other near the CLKM pin.
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In reply to jim s:
thanks for you answer
question about answer 1
i need the fpga and a2d to be clk synchronize to determine the sample in time for fpga
if the clks are separated there is a time uncertaintyof 1 clk .
is a low jitter zero delay buffer (1:2) a good solution for a low power system or is thare a better solution
just to be sure 1.8V clk LVCMOS voltage level is to be connected as clk input?
In reply to pablo glas:
A low jitter zero delay buffer is probably a good idea. I would still use the ADC output clock to register the data inside the FPGA though.
Yes, a 1.8V LVCMOS level clock input will work.
thanks for you answer
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