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ADS42JB69: Driving the SYNC~ pin with LVDS from Arria 10 FPGA

Prodigy 10 points

Replies: 2

Views: 63

Part Number: ADS42JB69

Hi, 

Our company is using ADS42JB69 to send data to FPGA.

I have read from the other post that we should use LVDS to drive SYNC~ and SYSREF pin for JESD204B on ADS42JB69.

However, from the Arria 10 FPGA (and the LMK04828) datasheet, the LVDS has a common voltage of 1.25V, with 1.125min and 1.375max.

But the datasheet of ADS42JB69 states that the input common mode voltage should be 0.9V. 

So I don't understand how this gonna work since we have this voltage difference and it's DC coupled.

Thank you so much!

2 Replies

  • Hi,

    We are looking at your question and will get back to you soon.

    Regards,

    Neeraj

  • Guru 54040 points

    Yinfei,

    Use a voltage divider on these lines to set the common mode to the correct level or use a translator device.

    Regards,

    Jim

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