Part Number: ADC12DJ3200
Customer would like to know the working of time-stamp signal of ADC12DJ3200.
I want to know the operating frequency of time-stamp signal.
Whether the frequency of time-stamp signal varies with sampling frequency.
Is it just logic i.e., time-stamp only required to be made high(1) or low(0) for all sampling frequency range.
I am planning to use Si5330 buffer in HCSL mode for interfacing FPGA and ADC12DJ3200 for meeting the common mode voltage and swing requirement of time-stamp signal pins.
The thing is Si5330 supports frequency range of 5-250Mhz only.
So if I use Si5330 for time-stamp pins of ADC12DJ3200, then I need to operate time-stamp signal in the frequency range of 5-250Mhz only.
We are looking into this.
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In reply to jim s:
I apologize for the delay.
The frequency of the time stamp signal is up to the user.
For instance if you plan to sample at 3200MSPS, then the period = 0.3125nSec.
If your time stamp signal is 250MHz, then the period = 4nSec
This means the trailing LSB will stay "high" for 12.8 cycles or (4n/0.3125n) to indicate the sampled analog input signal.
You can increase the frequency of the time signal if you choose in order to minimize the number of cycles that are indicated high.
Hope this helps.
High Speed Converter Group
Texas Instruments Inc.
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