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Interfacing a high speed ADC with a DSP

Prodigy 70 points

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I want to interface a high speed ADC such as the ADS5485 with a relatively low power DSP with sleep modes. The high speed ADCs tend to use LVDS outputs and DDR. A differential line receiver, such as the SN65LVDS9637 can convert LVDS to single ended LVTTL signals.

The questions I have are then:

Do any of TIs DSP have LVTTL compatible inputs?

Even after the data lines are converted to LVTTL, they will still be DDR. How do I interface DDR with a DSP? Do I need another intermediary IC? Can I use the DDR memory port on a DSP?

Now, suppose I want faster data rates with the ADC. Can I buffer the data in a chip and then send that data on to DSPs at a much slower rate in order to use much lower power DSPs? Do you have any suggestions for ICs that I can use in this case?

Any suggestions would be greatly appreciated.

 

  • Hi,

    I do not have a recommendation for a simple interface device that can translate LVDS to CMOS/TTL *and* change the format from DDR to single data rate - other than an FPGA.  There are relatively small and cheap FPGAs, but then there is the need to program them or have a small SPI eeprom that needs programming.

    The DSP chips do usually have an LVDS DDR bus for a memory interface, but I have not seen that used for ADC interface.  For one thing, there is usually a memory needed that is already using that bus so that it is not available for an ADC interface.  For specifics on connecting to an interface on one of the DSP chips, you would need to contact the forum for the DSP device directly.  I do not know if any of them have LVCMOS/LVTTL ports with DDR clocking.

    Almost always I see some glue-logic between the data converter and the DSP, and that is most often an FPGA.  If you do have to put an FPGA in the design, you would then have the flexibility to buffer and reformat the data into almost any format imaginable to then get it to your DSP.  For example, The TSW1200 that can capture data straight from the ADS5485EVM has an FPGA that can buffer up as much as 64K samples from the ADC to be offloaded later and over a slower interface.  The TSW1200 can capture data from our ADS5400 at 1Gsps, for an example of a capture from a higher sample rate device.  Newer FPGAs can have even more internal buffer capacity or faster speeds.

    Regards,

    Richard P.

  • In reply to Richard Prentice:

    I've often wondered about interfacing ADCs with DSP Chips.  It seems to me that if I need to put an FPGA on the board to accomplish this then why bother with the DSP chip.  I might as well do it all on the FPGA.  Then I only have one processing IC on the board instead of two. 

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