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ADS7863 with McBSP of a C2812.

Prodigy 30 points

Replies: 5

Views: 2485

Hi~ :)

I use ADS7863 with McBSP of a C2812.

The operation mode that I use is PSEUDO-DIFFERENTIAL MODE II.

I have a problem that communication error occurs by external noise during ADS7863 communication.

In case of normal operating state, the SDOA was shown as following order.

"Channel A(CHA0+/CHA0-) -> Channel B(CHB0+/CHB0-) -> Channel A(CHA1-/CHA0-) -> Channel B(CHB1-/CHB0-) -> … "

In case of abnormal operating state that communication error occurs, the SDOA was shown as following order despite CONVST, RD, and SDI were entered normally.

"Channel B -> Channel A -> Channel B -> Channel A -> …. " or "Channel A -> Channel A -> Channel B -> Channel A -> OR Channel A -> Channel A -> Channel B -> Channel A -> …"

Q1. Is it possible to solve this communication problem with software reset of ADS7863?

Q2. What is the difference between software reset and hardware reset?

 

Q3. If it is possible to solve the problem with software reset, could you inform us that the detail procedure of software reset.

 

Q4. As an additional question, there are additional features in table 5 and 6 in manual. Is it right to set the following parameters for device reset.

    P0:P0=[0:1], A2:A1:A0=[1:0:1]

5 Replies

  • Hi TaeHueong,

    While we look over your questions, could you possibly post a screen shot of your serial interface (SCLK, SDI, SDO, etc)?  Are you combining RD and CONVST, perhaps using the FSx output of the McBSP?

     

    Regards,

    Tom

  • In reply to Tom Hendrick:

    Hi Tom.

    I use that combining RD and CONVST.

    1. Normal Operation

     

    2. External Noise occurrence

    3. Normal Status -> Error Status(see. SDOA(channel changed))

     As I said earlier, I have some question.

    Is it possible to solve this communication problem with S/W reset of ADS7863?
    What is the difference between S/W reset and H/W reset?

    If it is possible to solve the problem with S/W reset, could you inform us that the detail procedure of S/W reset.

    As an additional question, there are additional features in table 5 and 6 in manual.
    Is it right to set the following parameters for device reset.
    P0:P0=[0:1], A2:A1:A0=[1:0:1]

    I will be looking forward to your prompt reply. :)

    Regards.

  • In reply to TaeHyeong Kim:

    Hi TaeHyeong,

    Both the software and hardware reset options put the ADS7863 back into its power on reset state.  Since this device does not have a physical 'reset' pin, power must be cycles to trigger the POR state.  A Software reset can be implemented at any time and is described in the last paragraph on page 28 of the data sheet.  There must be a RD pulse and reset command which involves setting bits A[2:0] to '101'.   Bits P[1:0] are necessary to be set in the 'update additional features' as you noted (set to '01'). 

    The noise disturbance you show in the pictures seems very dramatic.  What in your system causes that?  If that causes communication errors to the point where the ADS7863 is not responsive, it may be necessary to issue the SW reset twice.  The first time would re-establish serial communication and the second would ensure a full reset of the registers is complete.

     

    Regards,

    Tom

  • In reply to Tom Hendrick:

    Thank you for your answer.

    I have a additional question.

    In my case, when I reset the ADS7863 including setting bits P[1:0] to '01' ('set in the 'update additional features') , ‘reset’ operation doesn't work.

    But, when I reset to '00', ‘reset’ operation works.

    I don`t understand this abnormal operation.

    When the operating state of MC(Magnetic Contactor) is changed (ex. Case of 'On'->'Off' or 'Off'->'On'), noise is occurred. (Our system is three phase inverter system.(over 100kVA))

     Best regards.

  • In reply to TaeHyeong Kim:

    Hi Tae Hyeong,

    The PD bits should be set to 01.  Can you try and experiment for me by setting the DAC voltage to something other than 'FFF'?  Try '0FF' or some other value, read back the DAC register to ensure it's set to this new value and then do the SW reset.  The DAC should read back 'FFF' if the SW reset was successful.

     

    Regards,

    Tom

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