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TSW1200EVM vhdl

John Smith
Prodigy 10 points
Other Parts Discussed in Thread: ADS6149, ADS5463, ADS5281

I am evaluating this board with ADS4146EVM and noticed there is no enough files. Please, send me vhdl code and ucf file for TSW1200EVM at hdmb63@gmail.com. 

 

  • 0
    TI__Mastermind 29220 points

    Hi,

    Sent to the address provided.  We did not write the TSW1200 code in VHDL, but rather Verilog.  Also, i don't know what you mean by not enough files, as the source code is not normally provided with the hardware and User Interface but rather upon request.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Intellectual 600 points

    Dear sir.

    Can I receive verilog code & FPGA binary ?

    plz help me.

    popradtatri@gmail.com

  • 0 in reply to elsalvador
    TI__Mastermind 29220 points

    Hi,

    You've appended your request for the source code in two places, one was in reference to serialized data formats and this one which is in reference to parallel DDR data formats. I need to know whether you want the TSW1200 code for parallel DDR LVDS data formats or serialized LVDS data formats. 

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 20 points
    Hi,

    Can I get a Verilog top module with complete pin list and UCF file (for ISE) with pin assy and global constraints - all non related to a specific design.

    Thanks,
    Eli.
  • 0 in reply to Eli Goldman
    TI__Mastermind 29220 points

    Eli,

    when you say non-related to a specific design, I am guessing that our source code for the LVDS parallel bus format would be best suited.  The source code defines inputs to the FPGA for all the possible LVDS pairs that are listed in the schematics for the TSW1200 connector regardless of whether a specific EVM uses those inputs or leaves them floating.   Also the zip file includes the ucf file.    There are a few examples of timing constraint in the UCF for the DDR inputs, with one example for a source synchronous timing such as from our ADS5463 EVM and the other for a source centered timing such as our ADS6149.  But I believe Xilinx has changed the syntax since then for handing the DDR timing constraints.

    The other design database I could have sent would have been for our pseudo-serialized format such as our ADS5281, and the constraint file for that lists only as many as 10 LVDS inputs for just those inputs that are used by our highest channel count device.

    Anyway, if you would provide an email address to send it to I can send that out.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 20 points

    Hi Richard,
    Thank you for the prompt reply.

    You got a point there with the LVDS pins, I don't know yet if serial or parallel I/F will be used so best to have both examples.
    As for pin assignment and constraints I was not referring specifically to LVDS pins but a complete pinout (clocks, headers, leds, switches , lvds_pairs, etc ...)

    My email is: egoldman@airspan.com

    Appreciate your support.

    Thanks,

    Eli.

  • 0 in reply to Eli Goldman
    TI__Mastermind 29220 points

    Sent to the address provided.

    Regards,

    Richard P.