We are using the DDC112 in continuous mode at 15MHz clock speed. A external capacity of 250pF is used.
Ocassionally (after random powerup) the DDC does behave not as expected:
a) The 40 output data bit do contain first the IN1 signals instead of IN2.
b) Further the expected delay between toggling the CONV signal and the response of the DCC /DVALID is rougly 140us instead of 280.2us.See picture below.
We see a potential root cause in the sartup behavior of the board. The CONV signal and DXMIT signal insert aftefacts due to some level conversion. See picture below.
Are the power-up spikes the cause for the DDC misbehavior or are the other aspects to proove?
Thank you,
Samuel Zahnd