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ADC14DC080 / full-scale input and delay between DRDY and CLK output

S.Satoshi
Guru 21675 points
Other Parts Discussed in Thread: ADC14DC080

Hi,

I would like to ask two question for ADC14DC080 as below;

1,

In P3 and P14 of datasheet, it states that the differential full-scale input signal level is 2VP-P. But this ADC has 1.2V of internal VREF, then can we use 2.4VPP of input signal level? Or can we use input signal level by 2VPP if we will use 1.2V VREF?

2,

Could you please let us know the delay of DRDY output from CLK output? We could not find this information from datasheet.

Best Regards,

  • 0
    TI__Expert 4340 points

    The 1.2V internal reference corresponds to a 2Vpp-diff input range. Signals over 2Vpp will clip the ADC. If you provide an external 1.2V reference voltage, then the full scale range will still be 2.0V. When providing the reference externally, the range of acceptable voltages is narrow, so there is not much opportunity for varying the full scale input range on this ADC.

    The delay from CLK to DRDY is listed on the datasheet as 'Output delay of CLK to DATA' and is typically 6.7 ns.

    Regards, Josh

  • 0 in reply to Joshua Carnes
    Guru 21675 points

    Hi Josh-san,

    Thank you for your response for full-scale input range and delay from CLK to DRDY.

    Please let me ask again when I have additional question.

    Best Regards,

    Sonoki