Hi,
I've been working on an A to D converter design using the ADS1278. To this end, I've made a small prototype board to get familiar with the ADS1278 and associated components. This board is to be interfaced to an FPGA at a later date. However, I've run into a problem after populating this prototype board. The problem being that the DRDY pin is never pulsing low to indicate the data can be read out via SPI.
I'm using the ADS1278 in the following configuration:
FORMAT[2:0] = 010 (SPI data, discrete)
MODE[1:0] = 01 ( I wish to use High Resolution mode)
VREF = 2.5V
Input stages realised using OPA1632's - verified to work and then tied to ground to test the ADC
Clock provided by a crystal oscillator (3V3) at 27Mhz, scoped out and works fine with minimal jitter.
However the DRDY signal is always high and never pulses low. I've been trying to work out why this is so, I even connected an external function generator in place of the crystal and tried different CLK frequencies, but no luck.
I would be very grateful for any tips what else to look at to explain this lack of DRDY activity. Is there any other pin I can probe to verify the ADS1278 is alive and happy?
I have attached the relevant part of the schematic.
Finally, on an unrelated note, can someone please explain what relationship is required between CLK and SCLK? From what I've understood, as long as SCLK is at higher or equal frequency to CLK, the reads should come out correct, although it it is recommended to to keep SCLK/CLK ratio = 1/2, 1/4, 1/8, etc.
Thanks in advance for support.
Regards,
-Igor
