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ADS1292 - RLD External Reference

Bruce McMillan
Intellectual 310 points
Other Parts Discussed in Thread: ADS1292, ADS1292ECG-FE, ADS1292R

Technical Ref Doc states  (p.12) that if the RLDIN/RLDREF pin is not used it should be connected to AVdd. This appears to be incorrect. My investigation indicate that if irit is taken to AVdd then RLDout  is always near AVdd, irrespective of the setting if RLDREF (internal or external). It appears that RLDIN/RLDREF needs to be kept at near (AVdd-AVss)/2 - but then is left to wonder whether the RELREF int/ext switch actually works or not.

In the case of the ADS1292 Dev Boards, RELDIN/RLDREF is held at near the RLDout portential courtesy of a 100K resistor, obstensively there to allow the RLD signal to be fed to RLDIN for measurement, but it seems this is not optional.

RLDIN/RLDREF can be used as an auxiliary input to the MUX (a 4th input) and I had hoped to use it as such (and not for measuring RLD) however it seems one needs to be careful about how one does the biassing.

Appreciate id anyone out there has also come to the same conclusion.

tks, bruce

(love the chip)

  • 0
    TI__Guru**** 174266 points

    Hi Bruce,

    Thanks!  We'll double check the ADS1292ECG-FE schematics and the Users Guide and make changes if necessary.

  • 0
    TI__Mastermind 43915 points

    Hi Bruce,

    I did some modifications to the ADS1292ECG-FE board and tested the RLDIN/RLDREF pin while toggling the RLDREF_INT bit in the RESP2 register. It worked as expected here in the lab. I tied RLDREF to AVDD (3V in my system) and toggled the RLDREF_INT bit to see the RLD voltage change from 1.5V ((AVDD+AVSS) / 2) to 3V as that bit was changed from 0 to 1. Are you seeing differently in your system when that bit is toggled? You may want to try a read back command from the RESP2 to verify the bit is being set as expected.

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Intellectual 310 points

    Tony,

    Need to apologise then. Triple checked across two separate hardware boards (our design). Must be overwriting RESP2 in the firmware somewhere. I'll do as you suggest and read it back. 

    Very happy to be wrong.

    bruce

  • 0 in reply to Tony Calabria
    Intellectual 310 points

    Cry for help. ADS1292 - cosmological conspiracy? Two months on....

    To recap: on my board, RLDREF always appears to be in external reference mode.

    I had to 'put my fingers into the wounds' - I too tested the ADS1292ECG-FE board and it performs as Tony describes (and as expected): Namely, when the Reference of RLD is selected by the EVM software as internal, the voltage at RLDout is AVdd/AVss/2, and when changed to external reference, the voltage at RLDout will follow the voltage at RLDREF/RLDIN pin.

    On my board, on my second board that is - with completely redesigned layout - everything works fine. Signal capture, changing the Mux to turn on the internal test signal, turning the RLD buffer on and off, all are good. Indeed, reading back the Resp2 register says that the RLD amp is in internal Reference mode. I even sought out a chip of the same batch as that used on the ECG-FE board [It's never the silicon.]. However, no matter what I do, the chip behaves as if the RLD reference is external - the voltage at RLDout follows the voltage at RLDREF/RLDIN. And yet register read-back says it is in internal mode. [87H] Never yet seen Avdd-AVss/2 on the output tho. And yes, internal mode is the default!

    One would think the problem is hardware related - disconnected grounds maybe. But this is not a very complicated chip, and I have triple checked the deign. Must be a cosmological conspiracy. I welcome any thoughts.

    Details: Single supply AVdss = 4.5V. Reference: 4.0V. Clk 524kHz external. RLDOUT directly connected to RLDINV. RLDOUT directly connected to Voltmeter only. (this arrangement works on  ECG-FE board.

    Registers:

    ADS129x_CONFIG1 ;#00000000B        ; PN: continuous, 125sps (128sps)
    ADS129x_CONFIG2 ;#10110011B        ; PN: no lead-off ,enable ref buf, Vref=4V, no clk out, test sig
    ;ADS129x_LOFF, #10110010B               ; 
    ADS129x_CH1SET ;[ #01010000B        ; PN:[7:]enable,[6:4] PGA=8x,[3:0] mux:no test sig
    ADS129x_CH2SET , #01010000B         ; PN:[7:]enable,[6:4] PGA=8x,[3:0] mux:no test sig
    ADS129x_RLD_SENS , #00100000B    ; PN: [7:6]chop Fmod/16 (8kHz), [5:]RLD enable

    ; ADS129x_LOFF_SENS , #00000000B ; PN: disabled

    ;ADS129x_LOFF_STAT, #000000000B ; PN: b6:fclk=512kHz(default)
    ;ADS129x_RESP1 , #000000000B         ; data: resp off (default))
    ADS129x_RESP2 , #10000111B            ; PN: [7:]Calibr on, [2:]resp freq=64kHz, [1:]RLDRef internal(for slave?)
    ADS129x_GPIO , #00000010B                ; GPIO1:o/p, GPIO2: as o/p (no floating input)

  • 0 in reply to Bruce McMillan
    Prodigy 30 points

    Hi,

    I'm experiencing pretty much the same problem. Wrong RLDOUT voltage.

    I wonder if you have solved the problem,

    and I would really appreciate if you share the solution by leaving a reply to this post (http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/238212/834566.aspx#834566).

    Regards.

  • 0 in reply to Jongmoo Sohn
    Intellectual 355 points

    I got the same problem here too with a ADS1292R.  RLDOUT = AVdd = 3.3V, although I've only been at it for a hour or so and haven't gone thru the datasheet thoroughly yet.  I've left RLDIN/RLDREF and RLDINV float. I'm using 3.3V for both DVdd and AVdd.

    Got RLD_SENS=0x20 (RLD buffer enabled)
    and RESP2=0x03 (RLDREF_INT=1)
    Update: The external R and C components seem important even with RLDREF_INT=1. With the 1M resistor between RLDINV and RLDOUT as in Fig 48 (page 51) of the datasheet or like in the EVM schematics, I'm getting RLDOUT of 1.55V. Time to scrutinize the datasheet some more.
  • 0 in reply to Joe Desbonnet
    Intellectual 340 points

    Same problem happening for me. I am using +2.5V and -2.5V bipolar supply and RLD is railing at +2.5V. Did anyone solve this issue?

  • 0 in reply to ccent
    Intellectual 355 points

    My memory is hazy on this now, but if you look at he update to my post (30 Sep 2013, right before yours) I think I solved it by choosing the right external R and C.

  • 0 in reply to Joe Desbonnet
    Intellectual 340 points

    Thanks for the reply. After further testing, it seems the issue is related to the generation of the mid supply voltage on chip. Using bipolar supplies, the mid voltage generation is actually (|Avdd| + |AVss|)/2 giving (|+2.5| + |-2.5|)/2 = +2.5V. Using the 2.42V reference, this saturated the mid supply measurement and rails the RLD op amp. The datasheet has not been updated to reflect this yet and so it is quite misleading. Changing the reference to 4.03V does solve the mid-supply measurement issue, but does not seem to resolve the RLD output. I think the RLD op amp is powered from the +2.5V rail and so the RLD output is always +2.5V. The solution I am going to try is to tie RLDIN to gnd to provide a reference signal for the RLD close to the midsupply. 

    Corey