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ADS1256 SYNC timing requirements

Damien Dusha
Prodigy 190 points
Other Parts Discussed in Thread: ADS1256, ADS1255

Dear all,

I am looking at the ADS1256 and I am looking at Figure 3  in the datasheet.  It says that SYNC needs to be within +/- 25ns of the CLKIN (parameter t16B).

Since the ADC clock and the microcontroller clock (the uc pulses SYNC) on the design are independent, I am assuming I need an external synchronisation mechanism to ensure that the timing  requirements are met.   I am thinking of something like a two-stage D flip-flop clocked from D0/CLKOUT so that the output Q2 is sufficiently close to the CLKIN edge.  The second stage helps prevent instability in case the FF setup time is violated.

Is this the correct thing to do? Or is there a better way to approach this problem?

  -- Damien

  • 0
    TI__Mastermind 43915 points

    Hi Damien,

    The majority of the other ADCs are designed such that if the SYNC timing is not held, SYNC is simply delayed until the next master clock edge. The ADS1255/1256 is different. If the spec  timing is not met, the device may get into undocumented modes which were used as test modes.The T16B spec is crucial and we recommended a low cost single D Flip-flop to re-clock the SYNC edge to the rising master clock edge.

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Prodigy 190 points

    Hi Tony,

    Thank you for the clarification. Is metastability a problem with a single D flip-flop, given that setup time for the FF may well be violated?  Is there a specific family that prevents this problem?

      -- Damien

  • 0 in reply to Damien Dusha
    TI__Guru**** 180991 points

    Hi Damien,

    The minimum low period for the SYNC input (t16) to the ADS1256 is 4*tCLKIN cycles.  Assuming SYNC is asynchronous to the master clock, re-clocking through a DFF like the SN73LVC1G74 would require you to add an additional clock period to the width of the SYNC pulse so that you maintain the minimum length on the output of the flop.  I don't see where you would have any metastability issues here.