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ADS1259 settling time question

Q1. Why fclk 5.12MHz data rate slower than fclk 7.3728MHZ 14.4KSPS, but settling time shorter ~0.2944ms. When i changed the fclk and data rate.  How to calculate the settling time?

Thanks for your support ~~

 

Best regards,

Eric Lo

1) The ADS1259 is a Delta-sigma converter where the output data rate is a function of the master clock frequency.

The 4th order delta-sigma modulators samples the input signal at a rate of fclk/8.  The digital filter consists of two sections:The first section has a fixed decimation of 64, reducing the data rate of the modulator from fclk/8 to fclk/64.  The second section of the digital filter is a variable decimation filter configurable as sinc1 or sinc2 filter. The decimation ratio is programmable from 1 to 1440 by setting the DR[2:0] registers,

The data rate scales with the master clock frequency.  The device produces a 14400 SPS data rate using an fclk of 7.3728MHz; If the user requires a 10kSPS data rate, the user will have to use an external clock frequency of 5.12MHz.  The data sheet has some recommendations on pages 20 and 21 for the external clock source.

2)  The frequency response (notches) and settling time of the digital filter also scale with the CLK Frequency.  If the settling time with a data rate of 14.4kSPS is 0.424ms (fclk=7.3728MHz, sinc1); the settling time with a data rate of 10kSPS is ~0.2944ms (fclk=5.12MHz, sinc1)

  • Hi Eric,

    Yes, my apologies. The frequencies of the notches are direcly proportional to the clock frequency and the settling time is inversely proportional to the clock frequency; in other words, as you lower the master clock frequency, the frequencies of the notches are lower frequencies and the settling times are longer.

    If settling time at data rate of 14.4kSPS is 0.424ms (7.3728 MHz);  the settling time with a data rate of 10kSPS (fclk = 5.12MHz) is 30.5% longer; or ~0.553ms (not 0.2944)

    Thank you and Best Regards,

    Luis