Hi Team,
The ADS5485 is being used at 200 MHz. The differential clk amplitude is only 1.0Vpp. (Notice that this is below the recommended 1.5Vpp min)
What are the tradeoffs to having the differential clk amplitude set to 1.0Vpp as opposed to 1.5Vpp?
Over temperature, what is the absolute min that the clock Vpp must drive?
Best regards,
Brian Gosselin
Hi,
The tradeoff with lower clock amplitude is a possible loss of some SNR and some SFDR. At 1V p-p I doubt that you would see much degradation. You could use the figures in the datasheet to determine what a minimum clock amplitude would be acceptable for your application. The device would function with clock amplitude down to about 300mV but there would be some performance degradation.
Regards,
Richard P.
