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ADS4242 CLK input

Dwijen Pandya1
Prodigy 90 points
Other Parts Discussed in Thread: ADS4242

I am using ADS4242 for one of my design. If planning to used CMOS TCXO as clok input to the device. TCXO Voh = 2.97V (90% of 3.3V) and V0l = 0.33V (10% of 3.3V). TCXO output is connected through circuit in fig 164 on page 82 of datasheet.

Would this TCXO levels be sufficient to drive device? What is typical capacitive load on clk pin? What impedance would clock driver see? 

  • 0
    TI__Expert 8895 points

    Hi,

    For the better performance, we recommend to use differential clock input to ADS4242. The clock amplitude of single-ended clock is typically 1.5V and 0.1uF of capacitor is good enough for load. In our EVM, we use singled-ended clock source and converted it to differential using transformer. If you want, I can send you the schematic of our EVM.

    Thanks,

    KW