ADS1248 3 Channel Multiplexing following example

/*
 * main.c
 */

#include "msp430x54x.h"
#include "ads1248.h"
#include "puerto_serie.h"
#include <stdio.h>
#include <string.h>


int i,OK;
unsigned char dummy;
unsigned char valor[3];
unsigned char channel[3] = {0x01,0x13,0x25};

void ADS1248AssertCS(int fAssert)
{
   if (fAssert)
      P9OUT &= ~(ADS1248_CS);
   else
      P9OUT |=  ADS1248_CS;
}

int initSPIads1248(void)
{
  //Configuraci�n del puerto 9:
  //P9.1 UCB2SIMO -> Salida del master
  //P9.2 UCB2SOMI -> Entrada del master
  //P9.3 UCB2CLK -> Clock
  //P9.0 O -> ADS1248_CS, se activa a nivel bajo
  //P9.6 O -> ADS1248_START
  //P1.7 I <- ADS1248_DRDY, ACTIVAMOS LA IRQ DEL PUERTO 1.7

  P9DIR &= 0x30;
  P9DIR |= 0x41;
  P9SEL &= 0x30;
  P9SEL |= 0x0E;

  P1DIR &= 0x7F;
  P1DIR |= 0x00;
  P1SEL &= 0x7F;
  P1SEL |= 0x00;
  P1IE |= 0x80;                             // P1.7 interrupt enabled
  P1IES |= 0x80;                            // P1.7 Hi/Lo edge
  P1IFG &= ~0x80;                           // P1.7 IFG cleared

  //P8.6 O -> ADS1248_RESET, se activa a nivel bajo
  P8SEL &= 0x00;
  P8DIR &= 0x00;
  P8DIR |= 0x40;

  //PROBANDO
  UCB2CTL1 |= UCSWRST;

  //Definimos el registro de control: 8 bit, Modo Master, MSB se recibe primero, Modo Sincronico
  UCB2CTL0 |= UCMST + UCMSB + UCSYNC/* + UCCKPL*/;
  //Definimos el segundo registro de control: Fuente de Reloj SMCLK
  UCB2CTL1 |= UCSSEL_2;  // SMCLK
  //Pre-escalamos el Clk a SMCLK/8 = 8Mhz/8
  UCB2BR0 = 0x08; // /8 SMCLK/8 = 8Mhz/8 = 1MHz
  UCB2BR1 = 0;    //
  //UCB0MCTL = 0;  // No modulation
  //Habilitamos para que funcione el Modulo de Comunicacion
  UCB2CTL1 &= ~UCSWRST; // **Initialize USCI state machine**

  /*
  //LO AGREGAMOS PARA HABILITAR LA INTERRUPCION
  UCB2IE |= UCRXIE;                         // Enable USCI_B2 RX interrupt
   */

  return 0;
}

void init(void)
{
	WDTCTL = WDTPW + WDTHOLD;				// Stop WDT
	
	// Initialize LFXT1
	P7SEL |= 0x03;                            // Select XT1
	UCSCTL6 &= ~(XT1OFF);                     // XT1 On
	UCSCTL6 |= XCAP_3;                        // Internal load cap C=12.0pF

	// Loop until XT1 fault flag is cleared
	do
	{
	  UCSCTL7 &= ~XT1LFOFFG;                  // Clear XT1 fault flags
	}while (UCSCTL7&XT1LFOFFG);               // Test XT1 fault flag

	// Initialize DCO to 2.45MHz
	__bis_SR_register(SCG0);                  // Disable the FLL control loop
	UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
	UCSCTL1 = DCORSEL_6;                      // Set RSELx for DCO = 4.9 MHz
	UCSCTL2 = FLLD_1 + 243;                   // Set DCO Multiplier for 2.45MHz
	                                          // (N + 1) * FLLRef = Fdco
	                                          // (243 + 1) * 32768 = ___ MHz

	                                          // Set FLL Div = fDCOCLK/2
	__bic_SR_register(SCG0);                  // Enable the FLL control loop

	  // Worst-case settling time for the DCO when the DCO range bits have been
	  // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
	  // UG for optimization.
	  // 32 x 32 x 8 MHz / 32,768 Hz = 249856 = MCLK cycles for DCO to settle
	__delay_cycles(64000);
	__delay_cycles(64000);
	__delay_cycles(64000);
	__delay_cycles(64000);

}


void initRS232(void)
{
	P3SEL = 0x30;                           // P3.4,5 = USCI_A0 TXD/RXD

	UCA0CTL1 |= UCSWRST;                      // **Put state machine in reset**
	UCA0CTL1 |= UCSSEL_2;                     // CLK = DCO

	UCA0BR0 = 0x41;                           // ~8MHz/9600=833 (see User's Guide)
	UCA0BR1 = 0x03;                           //
	//UCA0MCTL = UCBRS_2+UCBRF_0;               // Modulation UCBRSx=2, UCBRFx=0
	UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
	//UCA0IE |= UCRXIE;                         // Enable USCI_A0 RX interrupt
}

void enviaRS232(unsigned char Code)
{
	while (!(UCA0IFG&UCTXIFG));             // USCI_A0 TX buffer ready?
	UCA0TXBUF = Code;
}


void main(void)
{

	OK=0;
	i=0;

	init();
	initRS232();
	initSPIads1248();

	//ADS1248 Power UP
	/************************/
	P9OUT |= ADS1248_START; 			//Start High
	P8OUT |= ADS1248_RESET; 			//Reset High
	ADS1248AssertCS(0);					//CS goes high
	while (!(UCB2IFG&UCTXIFG));			//DIN = 1
	UCB2TXBUF = 0x01;
	while (!(UCB2IFG&UCRXIFG));			//I ignore DOUT
	dummy=UCB2RXBUF;
	__delay_cycles(64000);
	__delay_cycles(1536);				//Delay of 2^16cycles = 8Mhz*65536 = 8ms
	/************************/

	//Issue RDATAC command to allow results to load into output register
	/************************/
	ADS1248AssertCS(1);					//CS goes low
	while (!(UCB2IFG&UCTXIFG));			//DIN = RDATAC command
	UCB2TXBUF = 0x14;
	while (!(UCB2IFG&UCRXIFG));			//I ignore DOUT
	dummy=UCB2RXBUF;
	/************************/

	//Configure channel CH0 AIN0:AIN1
	/************************/
	while (!(UCB2IFG&UCTXIFG));			//Write Register
	UCB2TXBUF = 0x40;					//0100 nnnn -> Direcci�n del primer registro a esbribir
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG));
	UCB2TXBUF = 0x0B;					//0000 nnnn -> n� de bytes a escribir - 1
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG));
	UCB2TXBUF = 0x01;					//MUX0  -> 00(Burnout current off)000(AIN0 as positive channel)001(AIN1 as negative channel)= 0000 0001
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG));
	UCB2TXBUF = 0x00;					//VBIAS -> 0, VBIAS not enabled
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG));
	UCB2TXBUF = 0x30;					//MUX1 -> 0 (Internal Oscilator) 01 (Internal reference always ON (necessary to use IDAC)) 10 (On board reference selected (Before 00 by defect)) 000 (Normal operation) 0011 0000
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG));
	UCB2TXBUF = 0x05;					//SYS0 -> 0 (por defecto) 000 (PGA=1) 0101 (160 SPS) = 0000 0101
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG)); 		//Offset calibration coefficient register, lo dejamos a =, por lo tanto una salida de 0 es equivalente a 0V
	UCB2TXBUF = 0x00;					//OFC0
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG));
	UCB2TXBUF = 0x00;					//OFC1
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG));
	UCB2TXBUF = 0x00;					//OFC2
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG));			//Full-scale calibration coefficient register, para un PGA = 1, ha de ser 0100 0000 0000 0000 0000 0000 = 0x400000
	UCB2TXBUF = 0x00;					//FSC0
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG));
	UCB2TXBUF = 0x00;					//FSC1
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG));
	UCB2TXBUF = 0x40;					//FSC2
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG));
	UCB2TXBUF = 0x00;					//IDAC0 -> xxxx (solo lectura) 0 (DOUT/DRDY solo como salida de datos) 000 (fuente de corriente decoenctada) = 0x00
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	while (!(UCB2IFG&UCTXIFG));
	UCB2TXBUF = 0xCC;					//IDAC1 -> 11xx 11xx (desconectadas) = 0xCC
	while (!(UCB2IFG&UCRXIFG));
	dummy=UCB2RXBUF;
	/************************/

	ADS1248AssertCS(0);					//CS goes high
	__bis_SR_register(GIE);				//Activo las Interrupciones

	while(1)
	{
		while(OK==0);					//Wait for falling edge of DRDYn

		while (!(UCB2IFG&UCTXIFG));
		UCB2TXBUF = 0x40;				//WREG 1 (0x40 -> el 0 corresponde a la direcci�n del primer Reg a escribir MUX0)
		while (!(UCB2IFG&UCRXIFG));
		valor[0]=UCB2RXBUF;				//MSB
		while (!(UCB2IFG&UCTXIFG));
		UCB2TXBUF = 0x40;				//WREG 2 (0x00 -> el 0 corresponde a que se escribir� 1 byte -1)
		while (!(UCB2IFG&UCRXIFG));
		valor[1]=UCB2RXBUF;				//2� data
		while (!(UCB2IFG&UCTXIFG));
		UCB2TXBUF = channel[i];			//Valor del registro MUX 0, ser� el siguiente canal
		while (!(UCB2IFG&UCRXIFG));
		valor[2]=UCB2RXBUF;				//LSB

		ADS1248AssertCS(0);					//CS goes high

		//Envio el resultado de la conversi�n por puerto serie
		enviaRS232(valor[0]);
		enviaRS232(valor[1]);
		enviaRS232(valor[2]);
	}
}



// Port 1 interrupt service routine
#pragma vector=PORT1_VECTOR
__interrupt void Port_1(void)
{
	OK=1; 						//Pongo el OK a 1 para poder continuar en el programa principal
	if (i==2){					//Cambiamos el valor del entero del vector que cambia de canal
		i=0;
	}
	else{
		i++;
	}
	ADS1248AssertCS(1);			//CS goes LOW
	P1IFG &= ~0x80;				// P1.7 IFG cleared

}