High speed differential line receivers

Hi,

If you want to ask questions about the different types of LVDS to single ended line drivers, you would need to ask that in the proper forum.  This is the high speed data converter forum.    But regardless, take a look at the switching characteristics of any of those line drivers, particularly the spec for output skew, and then look at the guaranteed setup and hold time for the data converters outptus relative to its bit clock.  At this kind of data rate you will find the the possible skews between any two outputs of the drivers will wipe out any setup/hold timing margin that you would need into your FPGA.   Max skews between outputs on the driver are on the order of 400ps or more.  Setup and hold times from the ADC are too tight for this kind of skew - for example at 50Msps, the ADS528x setup and hold times are given at 470ps and 650ps.  Subtracting out the max skew from the driver leaves no practical chance of ever meeting timing into the FPGA.  As I said yesterday, single ended signalling is not practical for these kind of data rates.  The datasheets for the buffers indicate a practical limit of about 200mbps, and you would have to ask in another forum to explain why one table would have a number of 630Mbps. 

Regards,

Richard P.

Hi,

Since that device you call out is only two-channel, you would not be able to fit all 10 of the LVDS signals from an ADS5281 into one buffer device adn so you would have to be converned with the 400ps part-to-part skew.   If you used a buffer that was 10bits or more in width then you would be able to run all 10 of the LVDS signals from one ADS5281 through a single buffer and then you would only have to consider the channel-to-channel skew in subtracting from your timing margin.  But either way, there is no way you would ever be able to make the FPGA close timing at anything anywhere near the max sample rate of the ADC using CMOS inputs to the FPGA, so again I must say I think you are wasting your time here.   And for that many ADS5281 devices in your system - each one would have to have its bit clock go to a clock-capable input on the FPGA to clock the other 9 signals (8 data signals and the frame clock) and I don't think you will have that many clock inputs on the FPGA anyway.

Regards,

Richard P.