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ADC12D1000 Master and Slave data timing

hisakichi kobayashi
Intellectual 950 points
Other Parts Discussed in Thread: ADC12D1000

Hi all.

There are the following questions about ADC12D1000.

1. At Time of Combination of One Master-ADC and One Slave-ADC, 
   For example, when one input signal is input into both a master and a slave,
   Are the data in which the signal sample of the master-ADC was carried out,
   and the data in which the signal sample of the slave-ADC was carried out outputted to the same timing with the almost same value?

2. Please let me know the input signal sampling of master and slave, and the details of data output timing.

3. Isn't there any graph to which the frequency of a CLK input and Jitter are related?.
   Moreover, doesn't a problem have a CLK input a sign wave?


Best regards,
Hisa Kobayashi.

  • 0
    TI__Mastermind 43910 points

    Hi Kobayashi-san

    1) The Autosync feature is intended to synchronize the output DATA and DCLK of multiple ADCs so that the data can more easily be captured, stored and processed. Additional information on the Autosync feature is available in this document: http://www.ti.com/lit/an/snaa073f/snaa073f.pdf  Additional factors affect the alignment of the sampling events in separate ADCs even if the input CLK signals are exactly aligned. Differences in the Aperture Delay parameter of each converter will result in some offset in the sampling instant between the multiple converters.

    2) The expected variation of Aperture Delay and data Output Delay due to process, temperature and supply voltage factors is described in section 3.3.4 of the document referenced above.

    3) The Jitter-SNR calculator at this link should provide what you are looking for: http://www.ti.com/tool/jitter-snr-calc It relates the Total Jitter, Aperture Jitter, Clock Jitter and maximum signal Input Frequency to expected SNR. Using a sine wave clock signal does not cause a problem as long as the jitter (from all sources including coupled noise, etc.) does not exceed the allowed clock jitter described in the calculator.

    I hope this is helpful.

    Best regards,

    Jim B

     

  • 0 in reply to Jim Brinkhurst1
    Intellectual 950 points

    Hi, Mr. Jim Brinkhurst84999.

    Thank you for your quick reply. I understood almost all the contents.
    However, please let me know the following contents.
    What kind of meaning is "in some offset in the sampling instant" by the text of the last of 1) ?
    Especially "some offset".

    Thank you for the helpful reply.

    Regards,
    Hisa Kobayashi.

  • 0 in reply to hisakichi kobayashi
    TI__Mastermind 43910 points

    Hi Kobayashi-san

    Assuming the input CLKs arrive at the ADC clock inputs exactly aligned, there can still be some difference in the Tad (aperture delay) time. This is the delay from the input clock edge to the actual internal sampling event. The difference in aperture delay from chip to chip will result in the sampling events occurring at slightly different times. From the datasheet, the typical aperture delay for the ADC12D1000 is 1.29 ns.

    From the Autosync application note, the expected variation of Tad from simulation is as follows:

    • Tad versus temperature (-40C to +85C ambient): +/-8.3%
    • Tad versus supply voltage (1.8V to 2.0V): +/-3.6%
    • Tad versus IC process variation: +/-19.2%
    • Tad versus all above sources of variation: +/-29.7% (Note: This composite variation modeling is smaller than the sum of the above individual sources).

    For simplicity we will consider the variation from all sources, which is +/- 29.7%. This will give a possible aperture delay range of 0.91ns to 1.67ns.

    However, if all ADC ICs are at the same ambient temperature and supply voltage, those effects can be eliminated. Then the remaining variation will be due to IC process variation. The +/-19.2% variation will result in an aperture delay range of 1.04ns to 1.54ns.

    I hope this is helpful.

    Best regards,

    Jim B

     

  • 0 in reply to Jim Brinkhurst1
    Intellectual 950 points

    Hi Jim-san,

    Thank you for the arrangement [ that it is serious and heaviness ].

    Regerds,

    Hisa Kobayashi.