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ADS8556 CONVST glitch - 2nd assertion of BUSY

Other Parts Discussed in Thread: ADS8556

Would the teeny tiny glitch on CONVST that is shown in my scope cap be the cause of the 2nd assertion of BUSY after the conversion cycle is done (which is ultimately causing lock-up in my design), even though the signal is nowhere near Vin min high for LVTTL or LVCMOS?  Does TI have recommendations, such as driving CONVST for the whole conversion cycle, feeding back BUSY and looking for this kind of behavior?  I found it to be really unexpected, and from power-cycle to power-cycle, it was not 100% reproducible, which makes me uncomfortable.


 

Document1.pdf
  • Hi Tom,

    Can you get a screen capture showing a little more detail?  Can you zoom in on the CONVST, and perhaps trigger on the falling edge?

  • I would love to be able to trigger the scope directly on the failure case, but unfortunately falling edge trigger on CONVST is not always the failure case.  It actually took quite a bit of time for me to manage to capture it on the scope even with the poor resolution shown.  I am continuously sampling the ADS8556 at 5KHz (200 usec) and sometimes the failure occurs as early as the 3rd sample from power-on reset (which is the only case where I can capture it) but it has occurred randomly during operation after many many cycles.  If I set my sampling interval on the scope high enough to get the detailed resolution of the event, I would be missing most events and could not guarantee capturing the one that causes the lock up.  The event that I want to capture is the last rising edge of BUSY prior to the chip no longer asserting BUSY.  Ideally, the ADS8556 would have a power down output signal that would tell me that I've tripped a shut down.  If that existed, I could 100% capture the event every time it happens by triggering on that.  Does that make sense?  Is there a backdoor that would help me to trigger on the inadvertent power-down?

  • Hi Tom,

    Unfortunately there is no back door trigger mechanism here.  Perhaps triggering on CONVST in 'pulse' type trigger that lasts less than 2us can capture more detail.  What is the purple trace in the screen shot you sent along?

  • The purple trace is RESET.

    For now, we seem to have things running well with higher valued damping / series termination resistors on the lines to the EVM board, thus suppressing those noise spikes a bit more than previously.