Would the teeny tiny glitch on CONVST that is shown in my scope cap be the cause of the 2nd assertion of BUSY after the conversion cycle is done (which is ultimately causing lock-up in my design), even though the signal is nowhere near Vin min high for LVTTL or LVCMOS? Does TI have recommendations, such as driving CONVST for the whole conversion cycle, feeding back BUSY and looking for this kind of behavior? I found it to be really unexpected, and from power-cycle to power-cycle, it was not 100% reproducible, which makes me uncomfortable.