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What could cause ADS8328 INT* to wedge asserted (low)?

Other Parts Discussed in Thread: ADS8328

Friends,

I designed the ADS8328 into an unattended field recorder product several years ago.  I worked around its quirks and have built over a 60 units but have never seen this event.  Unfortunately all I have to go on is a recorder's log file.

While acquiring data in manual trigger mode (i.e. hardware CONVST* is supplied) at a 232-kHz sample rate with an SPI clock of 8.7 MHz, it appears that the INT* pin failed to deassert after a sample.  The data sheet says that INT* "is set LOW at the end of a conversion is brought to HIGH (cleared) by the next read cycle."  Well I am confident the read cycle came along but it appears that INT* remained asserted (low).

The failure is not easily reproduced, it only just occurred for the first time after the design has gathered, cumulatively, years of data.  The only three things different from the past were (1) the CONVST* pulse train may have had missing pulses, though this is highly unlikely; (2) the ADS8328 was being run faster than typical applications, more often it is slower with sample rate 26 kHz and SPI clock 6.5 MHz; and (3) temperature was near freezing, most applications are at temperatures above 5C.

During the design process the ADS8328 did show a tendency to wedge during initialization in such a way that INT* was permanently asserted (low).  I learned that cycling analog power would un-wedge it.  But I never saw this happen during sampling.

Question:  Once setup is complete and many millions of correct samples have been successfully acquired, Is there any known cause for INT* to remain asserted even after read cycles for the present sample have commenced?  What if my 8. 7 MHz SPI interface was noisy?  Would that do it?  Or is 8.7 MHz too slow?

Thanks for any ideas!