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ADC14DC080 EVM layout pattern

Kuramochi Tadahiko
Guru 28715 points

Hi,

Figure 5.Layer 1: Component Side on  ADC14DC105EB and ADC12DC105EB Evaluation Boards is unclear.

So I can't see the detail.

Can I get the clear picture?

Insofar as I see the figure 5, DGND is connected with AGND nearby.

Should I divide the pattern like attached picture?

Thanks and Regards,

Kuramochi 

  • 0
    TI__Expert 4340 points

    Kuramochi,

    Yes, AGND and DGND should be a single ground on the EVM. You should not split the grounds under the EVM. The naming of DRGND and AGND is meaningful for bypassing. You should try to minimize the loop inductance from the VDR pin, through a bypass cap, and back to the DRGND pin. Similarly, you should minimize the loop from the VA pin, through the bypass cap, and back to an AGND pin.

     Regards, Josh