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ADC104S051 When does ADC change mode to Track mode?

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Hi

Could you tell me when ADC change mode from Hold mode to Track mode?
I think that ADC change from Hold mode to Track mode at 16th sclk of 16 sclk cycles.

I use ADC by the following setting.
- Sclk=3.3MHz
- CS become High level after 16th clk.
- length of CS high level is 20us~30us

In the above setting, I had issue.
Issue is that convert value is changed by previous IN value.
EX. Previous:IN1= 0.251V Next IN2 = 2.562V
Previous:IN1= 2.489V Next IN2 = 2.578V
I think that this cause is the memory effect.

But I changed CS time from "20us~30us" to "10ms".
Then This issue was improved.
EX. Previous:IN1= 0.246V Next IN2 = 2.571V
Previous:IN1= 2.489V Next IN2 = 2.572V

From this check, I think that ADC change from Hold mode to Track mode at 16th sclk of 16 sclk cycles.
I think long track mode is improved the memory effect.

Thanks
Shimizu

  • Hi How about progress? My customer need TI's answer.ThanksShimizu
  • In reply to masahiko shimizu:

    Shimizu-san,I am not sure if I fully understand your question.
    When does the ADC104S051 change from TRACK to HOLD mode? See data sheet page 16.
    The ADC104S051 is a successive-approximation analog-to-digital converter designed around a chargeredistribution
    digital-to-analog converter. Simplified schematics of the ADC104S051 in both track and hold modes
    are shown in Figure 47 Figure 48, respectively. In Figure 47, the ADC104S051 is in track mode: switch SW1
    connects the sampling capacitor to one of four analog input channels through the multiplexer, and SW2 balances
    the comparator inputs. The ADC104S051 is in this state for the first three SCLK cycles after CS is brought low.
    I believe your real question is answered on pg 17, Table 2
    These three bits determine which input channel will be sampled and converted in the next
    track/hold cycle. The mapping between codes and channels is shown in Table 4
    Hope this answers your question?Andreas
  • In reply to Andreas Kraemer:

    Hi Andress-san

    Thank you for your support.

    I want to know that When does the ADC104S051 change from HOLD to Track mode?

    Please see the attached file.

    Thanks

    Shimizu

    ADC104S051.pptx

  • Sorry, for my missunderstanding.See pg 17 data sheet:
    When CS is brought high, SCLK is internally gated off. If SCLK is stopped in the low state while CS is high, the
    subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track
    mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC
    enters the track mode on the first falling edge of SCLK after the falling edge of CS.
    Andreas
  • In reply to Andreas Kraemer:

    Hi Andress-san

    Thank you for your support.
    I understood that it's as datasheet mentioning.

    Thanks
    Shimizu

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