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  • TI Thinks Resolved

Inquiries regarding DAC8551

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Replies: 3

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Hello, all

Now we have some inquiries regarding DAC8551 from our customer.

Please refer to the items below, and feedback us with your comment.

Q1. Output voltage settling time

When referring "ELECTRICAL CHARACTERISTICS" on datasheet page 3, the Output voltage settling time is defined as 8us (typ) and 10us (max).

Please let us clarify whether this value is depended on the width of output transients.

Q2. Update late

When referring "/SYNC INTERRUPT" on datasheet page 16, we could understand that the DAC is updated on the 24th falling edge. This seems that the update time is 228us based on "(t5 + t6) * 24", which are described on datasheet page 5.

Please let us clarify whether the latency (delay) would be same as this.

We thank you in advance for your information.

Best regards, 

  • Hi Okui-san,

    Atsushi Okui
    Q1. Output voltage settling time

    What do you mean by if its dependent on the width of the output transients?

    The setting time includes the "dead time" and the "analog output transient settling". The dead time refers to the time from the digital update signal to 10% of the final output voltage. It does not include the SPI rate. The analog output transient settling is the time that it takes for the waveform to settle from 10% to 90% of the final output voltage.

    I would recommend that you take a look at this post by Kevin Duke DAC Essentials: Understanding your DAC speed limit.

    Atsushi Okui
    Q2. Update late

    The simplest way to calculate the max SPI rate is 24*SCLK_cycle = 24*(50ns) = 1.2us. This means that if you want to update the DAC as fast as possible while allowing it to settle, you can update the DAC every 1.2us + 10us = 11.2us. (maxSPI_rate + maxSettling_time)

    Hopefully this answers your questions. If this is still confusing, let me know and I will try to clarify it some more.

    > Eugenio Mejia

    Precision DAC Applications Engineer                 

  • In reply to Eugenio Mejia:

    Hello, Mejia-san, 

    Thank you for your prompt reply on the inquiry regarding DAC8551 from our customer.

    noticed that the datasheet specifies that the input variation for "Output voltage settling time" is fixed as "0200h to FD00h". There is no need to consider about output transients since the input validation is fixed.

    With regard to this term, please let us clarify about the following items;

    Q1. Please let us clarify whether you have any special consideration for the validation (8 to 10 us) for Output voltage settling time. 

    Q2. Please let us clarify about the reason why Output voltage settling time for "RL = 2kΩ, CL = 50 pF" condirion is higher than "RL = 2kΩ, 0pF < CL < 200pF" condition. It seems this (Typ 12us) should be the range of that (8 to 10 us). 

    We thank you once again for your information. 

    Best regards, 

  • In reply to Atsushi Okui:

    Okui -san,

    Atsushi Okui
    noticed that the datasheet specifies that the input variation for "Output voltage settling time" is fixed as "0200h to FD00h". There is no need to consider about output transients since the input validation is fixed.

    The DAC settling time is measure in the linear region of the DAC. The endpoints are affected by the same non-linear elements that amplifiers are affected by. This is why we don't measure from Zero-scale to Full-scale.

    Atsushi Okui

    Q1. Please let us clarify whether you have any special consideration for the validation (8 to 10 us) for Output voltage settling time. 

    Q2. Please let us clarify about the reason why Output voltage settling time for "RL = 2kΩ, CL = 50 pF" condirion is higher than "RL = 2kΩ, 0pF < CL < 200pF" condition. It seems this (Typ 12us) should be the range of that (8 to 10 us). 

    The datasheet does look confusing here. I am going to have the ask one of our systems engineers about how this data was originally taken. I will get back to you with more information.

    > Eugenio Mejia

    Precision DAC Applications Engineer                 

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