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We use multiple self clocking ADS1205, connected via isolation circuitry to multiple AMC1210.
To somewhat sync the data of various channels / AMC1210s - we use an external 4kHz sampleclock as S/H for AMC1210.
Because the ADS1205 are selfclocking - Sampleclock and modulatorclock are different time domains.
We use SOSR==32 for the filters - and the integrator in sample and hold mode IMOD=1.
Additionally, we read out the time-measure unit in mode1 for every channel.
After the rising edge of the sample clock - we read out the integrator and the tim.
The idea was that dividing the integrator value by (TIM/SOSR) should compensate for different # of integrations per external sampleclock.
10M / 32 = 312500 / 4000 = 78.125
If TIM is read between 2496 and 2527 - "78" should be the proper divisor.
But running with somewhat constant TIM@2500 - we experience few (est. 1/10) samples with lower readout - which can only be explained as that its not guaranteed that you got 78 filter values in the integrator during 2500 modulator clock cycles using SOSR==32.
I expect that if the filter update happens @ the rising edge of the sample clock - this value gets lost - and in the end we have TIM=2500 but only 77 filter values integrated.
Is this what happens ?
Some workaround could be to reduce SOSR - because this makes the error smaller - if happens.
Another option could be to use integrator oversampling mode - and reset the filter using MFE after every readout.
If all 4 modulators had the same clock - there would be the chance to sync the 4khz edge with the modulator clock -
but with 4 different freerunnig modulatorclocks - such a setup cannot work properly ?
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In reply to wolfgang gaerber:
I like this option best. Is it possible for you to sync your ADS1205 devices (how many are you using) together on the isolated side? If I read the first post correctly, you feed the outputs of your ADS1205 devices over an iso boundry to the AMC1210. The ADS1205 can take an external clock, so if they are in close proximity to each other, you could potentially use the CLKOUT from one device to feed the other modulator(s).
In reply to Tom Hendrick:
Hi Tom !
Did you mean my last idea with "I like this option best" ? - using s&h mode and apply a filter reset at the start of every period ?
All channels are isolated individually, so a primary synchronization is not feasible.
We could run the AMC1210 with an 8MHz quartz oscillator, locked to the sampling clock - and provide the modulator clock over the iso barrier.
Question would be if there is a problem with the phase delay introduced by the isolator circuit.
Yes, S&H mode with a parallel reset - and you probably will see some phase differences with all the modulators clocking themselves. If you could provide a common clock to the modulators, you may see some slight delay differences through your isolation, but I suspect it would be much less than what you see with them all clocking themselves.
Resetting the filter with integrator in S/H was no viable option - because we would need an additional integrator reset - and still suffered the problem that we cannot estimate the numbers of integrations derived from tim (this is needed because of frequency deviation of the self-clocking ads).
We finally decided to run without integrator at all - using 256times oversampling with the sinc3 filter. This gives us a jitter within +/-15us if we poll the last filter value from our sampleclock irq. So we run at 40kHz filter update rate and discard 90% of all updates - Because of a 400Hz LP on the input - this is no problem. We get rid of the artefacts caused by different time domain (which is 1.5% using SOSR32), now having few lsb variation@ 50% fullscale.
Additionally we have less delay - introduced by integrating the filter output - whats somehow interesting in our application.
Anyway - many thanks for your support.
The AMC1210 datasheet is not too verbose - and there should be some warning notice what might happen if clocked as slave.....
Its clear now from technical POV what happens - otherwise there could be internal circuitry which circumvents certain unwanted phase condition between S/H and clock input - but its not.
On some AMC1210 - we have isolated multichannel inputs - means we have 2 or more ADS1205 with one acting as clockmaster.
So in this cases - we have the same modulator clock on all channels of this AMC1210.
If I would synchronize the common S/H signal with this incomming modulator-clock by means of some glue logic - it should be possible to circumvent that race condition.
For such a solution I would need some more informations about AMC1210 internals.
1) How many modulator cycles/edges does it take from rising edge of sample hold to an integrator reset ?
2) How many modulator cycles/edges does it take to transfer / add a new filter value to the integrator.
Both values determine the "blind" spot - which is responsible for the situation that the measured tim doesnt correspond to filter cycles in the integrator.
If 1+2 would happen on the falling edge of modulator input clock - simple ANDing of S/H with modulator clock would be sufficient...
Is it possible to get more information regarding timing requirements of 1+2 if AMC1210 operated with external modulator clock ?
The only asynchronous input pin on the AMC1210 is RESET - pin 37, everything else is dependent on the modulator clock. Is it possible for you to gate (turn off) the integrator/modulator clock until all filter modules are configured? From there, set MFE and then turn on the modulator/integrator clock?
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